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2 1 - s3 - c9228/p9228-112002 user's manual s3c9228/p9228 8 -bit cmos microcontroller revision 1
s3c9228/p9228 8-bit cmos microcontroller s user's manual revision 1
important notice the information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein. samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes. this publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of samsung or others. samsung makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation any consequential or incidental damages. "typical" parameters can and do vary in different applications. all operating parameters, including " typicals" must be validated for each customer application by the customer's technical experts. samsung products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, for other applications intended to support or sustain life, or for any other application in which the failure of the samsung product could create a situation where personal injury or death may occur. should the buyer purchase or use a samsung product for any such unintended or unauthorized application, the buyer shall indemnify and hold samsung and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, expenses, and reasonable attorney fees arising out of, either directly or indirectly, any claim of personal injury or death that may be associated with such unintended or unauthorized use, even if such claim alleges that samsung was negligent regarding the design or manufacture of said product. s3c9228/p9228 8-bit cmos microcontroller s user's manual, revision 1 publication number: 2 1 - s3 - c9228/p9228 - 112002 ? 2002 samsung electronics all rights reserved. no part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of samsung electronics. samsung electronics' microcontroller business has been awarded full iso- 14 001 certification (b vqi certificate no 9330 ) all semiconductor products are designed and manufactured in accordance with the highest quality standards and objectives . samsung electronics co., ltd. san #24 nongseo- ri , kiheung-eup yongin-city, kyung g i-do, korea c.p.o. box #37, suwon 449-900 tel: ( 82 ) -(331)- 209- 1907 fax: (82)-(331)-209-1889 home-page url: http:// www. samsungsemi .com printed in the republic of korea
s3c9228/p9228 microcontroller s iii preface the s3c9228/p9228 microcontroller s user's manual is designed for application designers and programmers who are using the s3c9228/p9228 microcontroller s for application development. it is organized in two main parts: part i programming model part ii hardware descriptions part i contains software-related information to familiarize you with the microcontroller's architecture, programming model, instruction set, and interrupt structure. it has six chapter s: chapter 1 product overview chapter 2 address spaces chapter 3 addressing modes chapter 4 control registers chapter 5 interrupt structure chapter 6 sam88rcri instruction set chapter 1, "product overview," is a high-level introduction to the 100% with general product descriptions, as well as detailed information about individual pin characteristics and pin circuit types. chapter 2, "address spaces," explains the 100% program and data memory, internal register file, and mapped control register, and explains how to address them. chapter 2 also describes working register addressing, as well as system stack and user-defined stack operations. chapter 3, "addressing modes," contains detailed descriptions of the addressing modes that are supported by the cpu. chapter 4, "control registers," contains overview tables for all mapped system and peripheral control register values, as well as detailed one-page descriptions in standard format. you can use these easy-to-read, alphabetically organized, register descriptions as a quick-reference source when writing programs. chapter 5, "interrupt structure," describes the 100% interrupt structure in detail and further prepares you for additional information presented in the individual hardware module descriptions in part ii. chapter 6, " sam88rcri instruction set," describes the features and conventions of the instruction set used for all s3c9 -series microcontrollers. several summary tables are presented for orientation and reference. detailed descriptions of each instruction are presented in a standard format. each instruction description includes one or more practical examples of how to use the instruction when writing an application program. a basic familiarity with the information in part i will help you to understand the hardware module descriptions in part ii. if you are not yet familiar with the sam8 product family and are reading this manual for the first time, we recommend that you first read chapter s 1?3 carefully. then, briefly look over the detailed information in chapter s 4, 5, and 6. later, you can reference the information in part i as necessary. part ii "hardware descriptions," has detailed information about specific hardware components of the s3c9228/p9228 microcontrollers. also included in part ii are electrical, mechanical, otp, and development tools data. it has 13 chapter s: chapter 7 clock circuit s chapter 8 reset and power-down chapter 9 i/o ports chapter 10 basic timer chapter 11 timer 1 chapter 1 2 watch timer chapter 1 3 lcd controller/driver chapter 1 4 10-bit adc chapter 15 serial i/o interface chapter 16 electrical data chapter 17 mechanical data chapter 18 S3P9228 otp chapter 1 9 development tools two order forms are included at the back of this manual to facili t ate customer order for s3c9228/p9228 microcontrollers: the mask rom order form, and the mask option selection form. you can photocopy these forms, fill them out, and then forward them to your loca l samsung sales representative.

s3c9228/p9228 microcontroller s v table of contents part i ? programming model chapter 1 product overview sam88rcri product family ................................ ................................ ................................ ................... 1-1 s3c9228/p9228 microcontroller ................................ ................................ ................................ .............. 1-1 otp ................................ ................................ ................................ ................................ ......................... 1-1 features ................................ ................................ ................................ ................................ .................. 1-2 block diagram ................................ ................................ ................................ ................................ ......... 1-3 pin assignments ................................ ................................ ................................ ................................ ...... 1-4 pin descriptions ................................ ................................ ................................ ................................ ....... 1-6 pin circuit diagrams ................................ ................................ ................................ ................................ 1-8 chapter 2 address spaces overview ................................ ................................ ................................ ................................ ................. 2-1 program memory (rom) ................................ ................................ ................................ ......................... 2-2 register architecture ................................ ................................ ................................ ............................... 2 -3 common working register area (c0h?cfh) ................................ ................................ .......................... 2-4 system stack ................................ ................................ ................................ ................................ .......... 2-5 chapter 3 addressing modes overview ................................ ................................ ................................ ................................ ................. 3-1 register addressing mode (r) ................................ ................................ ................................ ......... 3-2 indirect register addressing mode (ir) ................................ ................................ ........................... 3-3 indexed addressing mode (x) ................................ ................................ ................................ .......... 3-7 direct address mode (da) ................................ ................................ ................................ ............... 3-10 relative address mode (ra) ................................ ................................ ................................ ........... 3-12 immediate mode (im) ................................ ................................ ................................ ...................... 3-12
vi s3c9228/p9228 microcontroller s table of contents (cont inued ) chapter 4 control registers overview ................................ ................................ ................................ ................................ ................. 4-1 chapter 5 interrupt structure overview ................................ ................................ ................................ ................................ ................. 5-1 interrupt processing control points ................................ ................................ ................................ .. 5-1 enable/disable interrupt instructions (ei, di) ................................ ................................ ................... 5-1 interrupt pending function types ................................ ................................ ................................ .... 5-2 interrupt priority ................................ ................................ ................................ ............................... 5-2 interrupt source service sequence ................................ ................................ ................................ . 5-3 interrupt service routines ................................ ................................ ................................ ............... 5-3 generating interrupt vector addresses ................................ ................................ ............................. 5-3 s3c9228/p9228 interrupt structure ................................ ................................ ................................ . 5-4 chapter 6 sam88rcri instruction set overview ................................ ................................ ................................ ................................ ................. 6-1 register addressing ................................ ................................ ................................ ......................... 6-1 addressing modes ................................ ................................ ................................ ........................... 6-1 flags register (flags) ................................ ................................ ................................ .................. 6-4 flag descriptions ................................ ................................ ................................ ............................. 6-4 instruction set notation ................................ ................................ ................................ ................... 6-5 condition codes ................................ ................................ ................................ .............................. 6-9 instruction descriptions ................................ ................................ ................................ .................... 6-10
s3c9228/p9228 microcontroller s vii table of contents (cont inued ) part ii ? hardware descriptions chapter 7 clock circui t overview ................................ ................................ ................................ ................................ ................. 7-1 system clock circuit ................................ ................................ ................................ ....................... 7-1 cpu clock notation ................................ ................................ ................................ ........................ 7-1 main oscillator circuits ................................ ................................ ................................ .................... 7-2 sub oscillator circuits ................................ ................................ ................................ ..................... 7-2 clock status during power-down modes ................................ ................................ ......................... 7-3 system clock control register (clkcon) ................................ ................................ ...................... 7-4 oscillator control register (osccon) ................................ ................................ ............................ 7-5 switching the cpu clock ................................ ................................ ................................ ................ 7-6 stop control register (stpcon) ................................ ................................ ................................ .... 7-7 chapter 8 reset reset and power-down system reset ................................ ................................ ................................ ................................ .......... 8-1 overview ................................ ................................ ................................ ................................ ......... 8-1 power-down modes ................................ ................................ ................................ ................................ . 8-2 stop mode ................................ ................................ ................................ ................................ ....... 8-2 idle mode ................................ ................................ ................................ ................................ ........ 8-3 hardware reset values ................................ ................................ ................................ ................... 8-4 chapter 9 i/o ports overview ................................ ................................ ................................ ................................ ................. 9-1 port data registers ................................ ................................ ................................ ......................... 9-2 port 0 ................................ ................................ ................................ ................................ .............. 9-3 port 1 ................................ ................................ ................................ ................................ .............. 9-6 port 2 ................................ ................................ ................................ ................................ .............. 9-9 port 3 ................................ ................................ ................................ ................................ .............. 9-11 port 4 ................................ ................................ ................................ ................................ .............. 9-14 port 5 ................................ ................................ ................................ ................................ .............. 9-15 port 6 ................................ ................................ ................................ ................................ .............. 9-16 chapter 10 basic timer overview ................................ ................................ ................................ ................................ ................. 10-1 basic timer control register (btcon) ................................ ................................ ........................... 10-2 basic timer function description ................................ ................................ ................................ .... 10-3
viii s3c9228/p9228 microcontroller s table of contents (con tinued ) chapter 11 timer 1 one 16-bit timer mode (timer 1) ................................ ................................ ................................ ............ 11-1 overview ................................ ................................ ................................ ................................ ......... 11-1 function description ................................ ................................ ................................ ........................ 11-1 two 8-bit timers mode (timer a and b) ................................ ................................ ................................ .. 11-4 overview ................................ ................................ ................................ ................................ ......... 11-4 function description ................................ ................................ ................................ ........................ 11-7 chapter 12 watch timer overview ................................ ................................ ................................ ................................ ................. 12-1 watch timer control register (wtcon) ................................ ................................ ......................... 12-2 watch timer circuit diagram ................................ ................................ ................................ ................... 12- 3 chapter 1 3 lcd controller/driver overview ................................ ................................ ................................ ................................ ................. 13-1 lcd circuit diagram ................................ ................................ ................................ ........................ 13-2 lcd ram address area ................................ ................................ ................................ .................. 13-3 lcd mode control register (lmod) ................................ ................................ ................................ 13-4 lcd port control register ................................ ................................ ................................ ............... 13-5 lcd voltage dividing resistors ................................ ................................ ................................ ....... 13-6 common (com) signals ................................ ................................ ................................ .................. 13-6 segment (seg) signals ................................ ................................ ................................ ................... 13-6 chapter 1 4 10-bit a/d converter overview ................................ ................................ ................................ ................................ ................. 14-1 function description ................................ ................................ ................................ ................................ 14-1 conversion timing ................................ ................................ ................................ .......................... 14-2 a/d converter control register (adcon) ................................ ................................ ....................... 14-2 internal reference voltage levels ................................ ................................ ................................ ... 14-3 block diagram ................................ ................................ ................................ ................................ ......... 14-3 chapter 1 5 serial i/o interface overview ................................ ................................ ................................ ................................ ................. 15-1 programming procedure ................................ ................................ ................................ .................. 15-1 sio control registers (siocon) ................................ ................................ ................................ ..... 15-2 sio pre-scaler register (siops) ................................ ................................ ................................ .... 15-3 sio block diagram ................................ ................................ ................................ ................................ .. 15-3 serial i/o timing diagram (sio) ................................ ................................ ................................ ...... 15-4
s3c9228/p9228 microcontroller s ix table of contents (con cluded ) chapter 1 6 electrical data overview ................................ ................................ ................................ ................................ ................. 16-1 chapter 1 7 mechanical data overview ................................ ................................ ................................ ................................ ................. 17-1 chapter 18 S3P9228 otp overview ................................ ................................ ................................ ................................ ................. 18-1 operating mode characteristics ................................ ................................ ................................ ....... 18-3 chapter 19 development tools overview ................................ ................................ ................................ ................................ ................. 19-1 shine ................................ ................................ ................................ ................................ ............. 19-1 sama assembler ................................ ................................ ................................ ............................ 19-1 sasm86 ................................ ................................ ................................ ................................ .......... 19-1 hex2rom ................................ ................................ ................................ ................................ ...... 19-1 target boards ................................ ................................ ................................ ................................ .. 19-1 tb9228 target board ................................ ................................ ................................ ...................... 19-3 idle led ................................ ................................ ................................ ................................ .......... 19-5 stop led ................................ ................................ ................................ ................................ ......... 19-5

s3c9228/p9228 microcontroller s xi list of figures figure title page number number 1-1 block diagram ................................ ................................ ................................ .................... 1-3 1-2 s3c9228 44-qfp pin assignments ................................ ................................ .................... 1-4 1-3 s3c9228 42-sdip pin assignments ................................ ................................ ................... 1-5 1-4 pin circuit type b ................................ ................................ ................................ .............. 1-8 1-5 pin circuit type c ................................ ................................ ................................ .............. 1-8 1-7 pin circuit type e-4 ................................ ................................ ................................ ........... 1-9 1-8 pin circuit type f-16 a ................................ ................................ ................................ ....... 1-9 1-9 pin circuit type h-23 ................................ ................................ ................................ ......... 1-10 1-10 pin circuit type h-32 ................................ ................................ ................................ ......... 1-11 1-11 pin circuit type h-32a ................................ ................................ ................................ ....... 1-11 1-12 pin circuit type h-32b ................................ ................................ ................................ ....... 1-12 2-1 s3c9228/p9228 program memory address space ................................ ............................. 2-2 2-2 internal register file organization ................................ ................................ ..................... 2-3 2-3 16-bit register pair s ................................ ................................ ................................ ........... 2-4 2-4 stack operations ................................ ................................ ................................ ................ 2-5 3-1 register addressing ................................ ................................ ................................ ........... 3-2 3-2 working register addressing ................................ ................................ ............................. 3-2 3-3 indirect register addressing to register file ................................ ................................ ...... 3-3 3-4 indirect register addressing to program memory ................................ ............................... 3-4 3-5 indirect working register addressing to register file ................................ ........................ 3-5 3-6 indirect working register addressing to program or data memory ................................ ..... 3-6 3-7 indexed addressing to register file ................................ ................................ ................... 3-7 3-8 indexed addressing to program or data memory with short offset ................................ ..... 3-8 3-9 indexed addressing to program or data memory with long offset ................................ ..... 3-9 3-10 direct addressing for load instructions ................................ ................................ ............... 3-10 3-11 direct addressing for call and jump instructions ................................ ................................ 3-11 3-12 relative addressing ................................ ................................ ................................ ............ 3-12 3-13 immediate addressing ................................ ................................ ................................ ........ 3-12 4-1 register description format ................................ ................................ ............................... 4-4
xii s3c9228/p9228 microcontroller s list of figures (cont inued ) figure title page number number 5-1 s3c9-series interrupt type ................................ ................................ ................................ 5-1 5-2 interrupt function diagram ................................ ................................ ................................ . 5-2 5-3 s3c9228/p9228 interrupt structure ................................ ................................ .................... 5-5 6-1 system flags register (flags) ................................ ................................ ......................... 6-4 7-1 crystal/ceramic oscillator ................................ ................................ ................................ .. 7-2 7-2 external oscillator ................................ ................................ ................................ .............. 7-2 7-3 rc oscillator ................................ ................................ ................................ ...................... 7-2 7-4 crystal/ceramic oscillator ................................ ................................ ................................ .. 7-2 7-5 external oscillator ................................ ................................ ................................ .............. 7-2 7-6 system clock circuit diagram ................................ ................................ ............................ 7-3 7-7 system clock control register (clkcon) ................................ ................................ ......... 7-4 7-8 oscillator control register (osccon) ................................ ................................ ............... 7-5 7-9 stop control register (stpcon) ................................ ................................ ..................... 7-7 9-1 s3c9228 i/o port data register format ................................ ................................ ............. 9-2 9-2 port 0 control register (p0con) ................................ ................................ ........................ 9-4 9-3 port 0 interrupt control register (p0int) ................................ ................................ ............ 9-4 9-4 port 0 interrupt pending bits (intpnd1.3-.0) ................................ ................................ ...... 9-5 9-5 port 0 interrupt edge selection register (p0edge) ................................ ............................ 9-5 9-6 port 0 pull-up control register ( p0pur) ................................ ................................ ............ 9-5 9-7 port 1 control register (p1con) ................................ ................................ ........................ 9-6 9-8 port 1 interrupt control register (p1int) ................................ ................................ ............ 9-7 9-9 port 1 interrupt pending bits (intpnd1.7-.4) ................................ ................................ ...... 9-7 9-10 port 1 interrupt edge selection register (p1edge) ................................ ............................ 9-8 9-11 port 1 pull-up control register (p1pur) ................................ ................................ ............ 9-8 9-12 port 2 control register (p2con) ................................ ................................ ........................ 9-9 9-13 port 2 pull-up control register (p2pur) ................................ ................................ ............ 9-10 9-14 port 3 control register (p3con) ................................ ................................ ........................ 9-11 9-15 port 3 interrupt control register (p3int) ................................ ................................ ............ 9-12 9-16 port 3 interrupt pending bits (intpnd2.5-.4) ................................ ................................ ...... 9-12 9-17 port 3 interrupt edge selection register (p3edge) ................................ ............................ 9-13 9-18 port 3 pull-up control register (p3pur) ................................ ................................ ............ 9-13 9-19 port 4 high-byte control register (p4conh) ................................ ................................ ..... 9-14 9-20 port 4 low-byte control register (p4conl) ................................ ................................ ....... 9-14 9-21 port 5 high-byte control register (p5conh) ................................ ................................ ..... 9-15 9-22 port 5 low-byte control register (p5conl) ................................ ................................ ....... 9-15 9-23 port 6 control register (p6con) ................................ ................................ ........................ 9-16
s3c9228/p9228 microcontroller s xiii list of figures (con tinued ) figure title page number number 10-1 basic timer control register (btcon) ................................ ................................ .............. 10-2 10-2 basic timer block diagram ................................ ................................ ................................ 10-4 11-1 timer 1 control register (tacon) ................................ ................................ ..................... 11-2 11-2 timer 1 block diagram (one 16-bit mode) ................................ ................................ ......... 11-3 11-3 timer a control register (tacon) ................................ ................................ .................... 11-5 11-4 timer b control register (tbcon) ................................ ................................ .................... 11-6 11-5 timer a block diagram (two 8-bit timers mode) ................................ ............................... 11-8 11-6 timer b block diagram (two 8-bit timers mode) ................................ ............................... 11-9 12-1 watch timer control register (wtcon) ................................ ................................ ............ 12-2 12-2 watch timer circuit diagram ................................ ................................ ............................. 12-3 13-1 lcd function diagram ................................ ................................ ................................ ....... 13-1 13-2 lcd circuit diagram ................................ ................................ ................................ .......... 13-2 13-3 lcd display data ram organization ................................ ................................ ................. 13-3 13-4 lcd mode control register (lmod) ................................ ................................ .................. 13-4 13-5 lcd port control register ................................ ................................ ................................ .. 13-5 13-6 internal voltage dividing resistor connection ................................ ................................ .... 13-6 13-7 lcd signal waveforms (1/8 duty, 1/4 bias) ................................ ................................ ....... 13-7 13-8 lcd signal waveforms (1/4 duty, 1/3 bias) ................................ ................................ ....... 13-8 13-9 lcd signal waveforms (1/3 duty, 1/3 bias) ................................ ................................ ....... 13-9 14-1 a/d converter control register (adcon) ................................ ................................ .......... 14-2 14-2 a/d converter data register (addatah/addatal) ................................ ......................... 14-3 14-3 a/d converter functional block diagram ................................ ................................ ........... 14-3 14-4 recommended a/d converter circuit for highest absolute accuracy ................................ . 14-4 15-1 serial i/o module control register (siocon) ................................ ................................ .... 15-2 15-2 sio prescaler register (siops) ................................ ................................ ......................... 15-3 15-3 sio functional block diagram ................................ ................................ ............................ 15-3 15-4 serial i/o timing in transmit/receive mode (tx at falling, siocon.4 = 0) ........................ 15-4 15-5 serial i/o timing in transmit/receive mode (tx at rising, siocon.4 = 1) ......................... 15-4
xiv s3c9228/p9228 microcontroller s list of figures (con cluded ) figure title page number number 16-1 stop mode release timing when initiated by an external interrupt ................................ .... 16-5 16-2 stop mode release timing when initiated by a reset ................................ ..................... 16-6 16-3 input timing for external interrupts ................................ ................................ ..................... 16-8 16-4 input timing for reset ................................ ................................ ................................ ...... 16-9 16-5 se rial data transfer timing ................................ ................................ ................................ 16-9 16-6 clock timing measurement at x in ................................ ................................ ..................... 16-11 16-7 clock timing measurement at xt in ................................ ................................ ................... 16-12 16-8 operating voltage range ................................ ................................ ................................ ... 16-13 17-1 42-sdip-600 package dimensions ................................ ................................ ..................... 17-1 17-2 44-qfp-1010b package dimensions ................................ ................................ .................. 17-2 18-1 S3P9228 44-qfp pin assignments ................................ ................................ .................... 18-1 18-2 s3p 9228 42-sdip pin assignments ................................ ................................ ................... 18-2 18-3 standard operating voltage range ................................ ................................ .................... 18-5 19-1 smds product configuration (smds2+) ................................ ................................ ............ 19-2 19-2 tb9228 target board configuration ................................ ................................ ................... 19-3 19-3 connectors (j101, j102) for tb9228 ................................ ................................ .................. 19-6 19-4 s3c9228 probe adapter for 42-sdip package ................................ ................................ ... 19-7 19-5 s3c9228 probe adapter for 44-qfp package ................................ ................................ .... 19-7
s3c9228/p9228 microcontroller s xv list of tables table title page number number 1-1 pin descriptions ................................ ................................ ................................ ................. 1-6 6-1 instruction group summary ................................ ................................ ................................ 6-2 6-2 flag notation conventions ................................ ................................ ................................ . 6-5 6-3 instruction set symbols ................................ ................................ ................................ ...... 6-5 6-4 instruction notation conventions ................................ ................................ ........................ 6-6 6-5 opcode quick reference ................................ ................................ ................................ ... 6-7 6-6 condition codes ................................ ................................ ................................ ................. 6-9 8-1 register values after reset ................................ ................................ ............................. 8-4 9-1 s3c9228 port configuration overview ................................ ................................ ............... 9-1 9-2 port data register summary ................................ ................................ .............................. 9-2 13-1 common and segment pins per d uty cycle ................................ ................................ ....... 13-3 16-1 absolute maximum ratings ................................ ................................ ................................ 16-2 16-2 d.c. electrical characteristics ................................ ................................ ............................ 16-2 16-3 data retention supply voltage in stop mode ................................ ................................ ..... 16-5 16-4 input/output capacitance ................................ ................................ ................................ ... 16-6 16-5 a.c. electrical characteristics ................................ ................................ ............................ 16-7 16-6 a /d converter electrical characteristics ................................ ................................ ............. 16-8 16-7 main oscillation characteristics ................................ ................................ .......................... 16-10 16-8 sub oscillation characteristics ................................ ................................ ........................... 16-10 16-9 main oscillation stabilization time ................................ ................................ ..................... 16-11 16-10 sub oscillation stabilization time ................................ ................................ ...................... 16-12 18-1 descriptions of pins used to read/write the eprom ................................ ......................... 18-3 18-2 comparison of S3P9228 and s3c9228 features ................................ ................................ 18-3 18-3 operating mode selection criteria ................................ ................................ ...................... 18-3 18-4 d.c. electrical characteristics ................................ ................................ ............................ 18-4 19-1 power selection settings for tb9228 ................................ ................................ .................. 19-4 19-2 the smds2+ tool selection setting ................................ ................................ .................. 19-5 19-3 using single header pins as the input path for external trigger sources ........................... 19-5

s3c9228/p9228 microcontroller s xvii list of programming tips description page number chapter 2: address spaces addressing the common working register area ................................ ................................ ..................... 2-4 standard stack operations using push and pop ................................ ................................ .................. 2-6 chapter 5 : interrupt structure how to clear an interrupt pending bit ................................ ................................ ................................ ........ 5-6 chapter 7 : clock circuits switching the cpu clock ................................ ................................ ................................ .......................... 7-6 how to use stop instruction ................................ ................................ ................................ ..................... 7-7

s3c9228/p9228 microcontroller s xix list of register descriptions register full register name page identifier number adcon a/d converter co ntrol register ................................ ................................ .............. 4-5 btcon basic timer control register ................................ ................................ ................. 4-6 clkcon system clock control register ................................ ................................ ............... 4-7 flags system flags register ................................ ................................ ........................... 4-8 intpnd1 interrupt pending register 1 ................................ ................................ ................... 4-9 intpnd2 interrupt pending register 2 ................................ ................................ ................... 4-10 lmod lcd mode control register ................................ ................................ ................... 4-11 lpot lcd po rt control register ................................ ................................ ...................... 4-12 osscon oscillator control register ................................ ................................ ..................... 4-13 p0con port 0 control register ................................ ................................ ........................... 4-14 p0int port 0 interrupt enable register ................................ ................................ ............. 4-15 p0pur port 0 pull-up resistors enable register ................................ ................................ 4-16 p0edge port 0 interrupt edge selection register ................................ ................................ 4-17 p1con port 1 control register ................................ ................................ ........................... 4-18 p1int port 1 interrupt enable register ................................ ................................ ............. 4-19 p1pur port 1 pull-up resistors enable register ................................ ................................ 4-20 p1edge port 1 interrupt edge selection register ................................ ................................ 4-21 p2con port 2 control register ................................ ................................ ........................... 4-22 p2pur port 2 pull-up resistors enable regist er ................................ ................................ 4-23 p3con port 3 control register ................................ ................................ ........................... 4-24 p3int port 2 interrupt enable register ................................ ................................ ............. 4-25 p3pur port 3 pull-up resistors enable register ................................ ................................ 4-26 p3edge port 3 interrupt edge selection register ................................ ................................ 4-27 p4conh port 4 control register ................................ ................................ ........................... 4-28 p4conl port 4 control register low byte ................................ ................................ ........... 4-29 p5conh port 5 control register high byte ................................ ................................ .......... 4-30 p5conl port 5 control register low byte ................................ ................................ ........... 4-31 p6con port 6 control register ................................ ................................ ........................... 4-32 siocon sio control register ................................ ................................ .............................. 4-33 stpcon stop control register ................................ ................................ ............................. 4-34 sym system mode register ................................ ................................ ........................... 4-35 tacon timer 1/a control register ................................ ................................ ..................... 4-36 tbcon timer b control register ................................ ................................ ........................ 4-37 wtcon watch timer control register ................................ ................................ ................ 4-38

s3c9228/p9228 microcontroller s xxi list of instruction descriptions instruction full instruction name page mnemonic number adc add with carry ................................ ................................ ................................ ...... 6 - 1 1 add add ................................ ................................ ................................ ........................ 6-12 and logical and ................................ ................................ ................................ ........... 6-13 call call procedure ................................ ................................ ................................ ....... 6-14 ccf complement carry flag ................................ ................................ ......................... 6-15 clr clear ................................ ................................ ................................ ...................... 6-16 com complement ................................ ................................ ................................ .......... 6-17 cp compare ................................ ................................ ................................ ................ 6-18 dec decrement ................................ ................................ ................................ ............. 6-19 di disable interrupts ................................ ................................ ................................ ... 6-20 ei enable interrupts ................................ ................................ ................................ .... 6-21 idle idle operation ................................ ................................ ................................ ........ 6-22 inc increment ................................ ................................ ................................ ............... 6-23 iret interrupt return ................................ ................................ ................................ ...... 6-24 jp jump ................................ ................................ ................................ ...................... 6-25 jr jump relative ................................ ................................ ................................ ........ 6-26 ld load ................................ ................................ ................................ ...................... 6-27 ldc/lde load memory ................................ ................................ ................................ ......... 6- 29 ldcd/lded load memory and decrement ................................ ................................ ................ 6-31 ldci/ldei load memory and increment ................................ ................................ ................. 6-32 nop no operation ................................ ................................ ................................ ......... 6-33 or logical or ................................ ................................ ................................ ............. 6-34 pop pop from stack ................................ ................................ ................................ ..... 6-35 push push to stack ................................ ................................ ................................ ....... 6-36 rcf reset carry flag ................................ ................................ ................................ .... 6-37 ret return ................................ ................................ ................................ .................... 6-38 rl rotate left ................................ ................................ ................................ ............. 6-39 rlc rotate left through carry ................................ ................................ ...................... 6-40 rr rotate right ................................ ................................ ................................ ........... 6-41 rrc rotate right through carry ................................ ................................ ................... 6-42 sbc subtract with carry ................................ ................................ ............................... 6-43 scf set carry flag ................................ ................................ ................................ ........ 6-44 sra shift right arithmetic ................................ ................................ ............................. 6-45 stop stop operation ................................ ................................ ................................ ....... 6-46 sub subtract ................................ ................................ ................................ ................. 6-47 tcm test complement under mask ................................ ................................ ............... 6-48 tm test under mask ................................ ................................ ................................ .... 6-49 xor logical exclusive or ................................ ................................ ............................. 6-50
s3c9228/p9228 product overview 1- 1 1 product overview sam8 8rc ri product family samsung's sam88rcri family of 8-bit single-chi p cmos microcontrollers offer fast and efficient cpu, a wide range of integrated peripherals, and supports otp device . a dual address/data bus architecture and bit- or nibble-configurable i/o ports provide a flexible programming environment for applications with varied memory and i/o requirements. timer/counters with selectable operating modes are included t o support real-time operations. s3c9228/p9228 microcontroller the s3c9228 can be used for dedicated control functions in a variety of applications, and is especially designed for application with frs or etc. the s3c9228/p9228 single-chip 8-bit microcontroller is fabricated using an advanced cmos process. it is built around the powerful sam88rcri cpu core. stop and idle power-down modes were implemented to reduce power consumption. to increase on-chip register space, the size of the internal register file was logically expanded. the s3c9228/p9228 has 8k-byte of program rom, and 264-byte of ram (including 16-byte of working register and 20-byte lcd display ram). using the sam 88rcri design approach, the following peripherals were integrated with the sam88rcri core: ? 7 configurable i/o ports including ports shared with segment/common drive outputs ? 10-bit programmable pins for external interrupts ? one 8-bit basic timer for oscillation stabilization and watch-dog functions ? two 8-bit timer/counters with selectable operating modes ? watch timer for real time ? 4 channel a/d converter ? 8-bit serial i/o interface otp the s3c9228 microcontroller is also available in otp (one time programmable) version. S3P9228 microcontroller has an on-chip 8k-byte one-time-programmable eprom instead of masked rom. the S3P9228 is comparable to s3c9228 , both in function and in pin configuration.
product overview s3c9228/p9228 1- 2 features cpu sam88rcri cpu core memory 8192 8 bits program memory (rom) 264 8 bits data memory (ram) (including lcd data memory) instruction set 41 instructions idle and stop instructions added for power-down modes 36 i/o pins i/o: 34 pins (44-pin qfp, 42-pin sdip) output only: 2 pins (44-pin qfp) interrupts 14 interrupt source and 1 vector one interrupt level 8-bit basic timer watchdog timer function 3 kinds of clock source two 8-bit timer/counters the programmable 8-bit timer/counters external event counter function configurable as one 16-bit timer/counters watch timer interval time: 3.91ms, 0.25s, 0.5s, and 1s at 32.768 khz 0.5/1/2/4 khz selectable buzzer output clock source generation for lcd lcd controller/driver 16 segments and 8 common terminals 3, 4, and 8 common selectable internal resistor circuit for lcd bias 8-bit serial i/o interface 8-bit transmit/receive mode 8-bit receive mode lsb-first or msb-first transmission selectable internal or external clock source a/d converter 10-bit converter resolution 50us conversion speed at 1mhz f adc clock 4-channel two power-down modes idle: only cpu clock stops stop: system clock and cpu clock stop oscillation sources crystal, ceramic, or rc for main clock main clock frequency: 0.4 mhz - 8mhz 32.768 khz crystal oscillation circuit for sub clock instruction execution times 500ns at 8mhz fx(minimum) operating voltage range 2.0 v to 5.5 v at 0.4 - 4.2mhz 2.7 v to 5.5 v at 0.4 - 8mhz operating temperature range -25 c to +85 c package type 44-pin qfp, 42-pin sdip
s3c9228/p9228 product overview 1- 3 block diagram 8-bit timer/ countera port i/o and interrupt control sam88rcri cpu reset x in xt in i/o port 0 8-kbyte rom 264-byte register file x out xt out 16-bit timer/ counter1 8-bit timer/ counterb taout/ p0.0 t1clk/ p0.1 p0.0/taout/int p0.1/t1clk/int p0.2/int p0.3/buz/int p0.4 p0.5 i/o port 1 p1.0/ad0/int p1.1/ad1/int p1.2/ad2/int p1.3/ad3/int i/o port 2 p2.0/sck/seg1 p2.1/so/seg0 p2.2/si p2.3 i/o port 3 p3.0/intp/seg3 p3.1/intp/seg2 i/o port 4 p4.0-p4.7/ seg4-seg11 i/o port 5 p5.0-p5.3/ seg12-seg15 p5.4-p5.7/ seg16-seg19/ com7-com4 watchdog timer basic timer watch timer lcd driver/ controller sio a/d converter com0-com3/p6.3-p6.0 com4-com7/ seg19-seg16/p5.7-p5.4 seg0-seg1/p2.1-p2.0 seg2-seg3/p3.1-p3.0 seg4-seg11/p4.0-p4.7 p2.0/sck/seg1 p2.1/so/seg0 p2.2/si buz/p0.3 p1.0-p1.3/ad0-ad3 seg12-seg15/p5.0-p5.3 i/o port 6 p6.0-p6.3/com3-com0 figure 1-1. block diagram
product overview s3c9228/p9228 1- 4 pin assignments 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 s3c9228 (44-qfp) p1.0/ad0/int p1.1/ad1/int p1.2/ad2/int p1.3/ad3/int v dd v ss x out x in test xt in xt out reset p2.3 p2.2/si seg0/p2.1/so seg1/p2.0/sck seg2/p3.1/intp seg3/p3.0/intp seg4/p4.0 seg5/p4.1 seg6/p4.2 seg7/p4.3 33 32 31 30 29 28 27 26 25 24 23 com5/seg18/p5.6 com6/seg17/p5.5 com7/seg16/p5.4 seg15/p5.3 seg14/p5.2 seg13/p5.1 seg12/p5.0 seg11/p4.7 seg10/p4.6 seg9/p4.5 seg8/p4.4 44 43 42 41 40 39 38 37 36 35 34 p0.5 p0.4 p0.3/buz/int p0.2/int p0.1/t1clk/int p0.0/taout/int com0/p6.3 com1/p6.2 com2/p6.1 com3/p6.0 com4/seg19/p5.7 figure 1-2. s3c9228 44-qfp pin assignments
s3c9228/p9228 product overview 1- 5 com1/p6.2 com0/p6.3 p0.0/taout/int p0.1/t1clk/int p0.2/int p0.3/buz/int p1.0/ad0/int p1.1/ad1/int p1.2/ad2/int p1.3/ad3/int v dd v ss x out x in test xt in xt out reset p2.3 p2.2/si seg0/p2.1/so s3c9228 (42-sdip) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 com2/p6.1 com3/p6.0 com4/seg19/p5.7 com5/seg18/p5.6 com6/seg17/p5.5 com7/seg16/p5.4 seg15/p5.3 seg14/p5.2 seg13/p5.1 seg12/p5.0 seg11/p4.7 seg10/p4.6 seg9/p4.5 seg8/p4.4 seg7/p4.3 seg6/p4.2 seg5/p4.1 seg4/p4.0 seg3/p3.0/intp seg2/p3.1/intp seg1/p2.0/sck 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 figure 1-3. s3c9228 42-sdip pin assignments
product overview s3c9228/p9228 1- 6 pin descriptions table 1- 1 . pin descriptions pin names pin type pin description circuit number pin numbers share pins p0.0 p0.1 p0.2 p0.3 i/o 1-bit programmable i/o port. schmitt trigger input or push-pull, open-drain output and software assignable pull-ups. e-4 39(3) 40(4) 41(5) 42(6) taout/int t1clk/int int buz/int p0.4-p0.5 o 1-bit programmable output port. c 43-44 p1.0 p1.1 p1.2 p1.3 i/o 1-bit programmable i/o port. schmitt trigger input or push-pull, open-drain output and software assignable pull-ups. f-16a 1(7) 2(8) 3(9) 4(10) ad0/int ad1/int ad2/int ad3/int p2.0 p2.1 i/o 1-bit programmable i/o port. schmitt trigger input or push-pull, open-drain h-32a 16(22) 15(21) sck/seg1 so/seg0 p2.2 p2.3 i/o output and software assignable pull-ups. e-4 14(20) 13(19) si ? p3.0 p3.1 i/o 1-bit programmable i/o port. schmitt trigger input or push-pull, open-drain output and software assignable pull-ups. h-32b 18(24) 17(23) intp/seg3 intp/seg2 p4.0?p4.7 i/o 1-bit programmable i/o port. input or push-pull, open-drain output and software assignable pull-ups. h-32 19-26(25-32) seg4-seg11 p5.0?p5.3 i/o 1-bit programmable i/o port. input or push-pull, open-drain output and h-32 27-30(33-36) seg12-seg15 p5.4?p5.7 software assignable pull-ups. 31-34(37-40) seg16-seg19 /com7-com4 p6.0-p6.3 i/o 1-bit programmable i/o port. input or push-pull, open-drain output and software assignable pull-ups. h-32 35-38 (41-42,1-2) com3-com0 note: parentheses indicate pin number for 42-sdip-600 package.
s3c9228/p9228 product overview 1- 7 table 1- 1 . pin descriptions (continued) pin names pin type pin description circuit number pin numbers share pins v dd , v ss ? power input pins for internal power block ? 5,6(11,12) ? x out , x in ? main oscillator pins for main clock ? 7,8(13,14) xt out , xt in ? sub oscillator pins for sub clock ? 11,10(17,16) ? test ? chip test input pin hold gnd when the device is operating ? 9(15) ? reset i reset signal input pin. schmitt trigger input with internal pull-up resistor. b 12(18) ? int i/o external interrupts input. e-4 f-16a 39-42(3-6) 1-4(7-10) p0.0-p0.3 p1.0-p1.3 intp i/o key scan interrupts inputs. h-32b 17-18(23-24) p3.1-p3.0 t1clk i/o timer 1/a external clock input. e-4 40(4) p0.1 taout i/o timer 1/a clock output. e-4 39(3) p0.0 ad0-ad3 i/o analog input pins for a/d converts module. f-16a 1-4(7-10) p1.0-p1.3 buz i/o buzzer signal output. e-4 42(6) p0.3 sck so i/o serial clock, serial data output, serial data input h-32a 16-15(22-21) p2.0-p2.1 si e-4 14(20) p2.2 seg0-seg1 i/o lcd segment signal output h-32a 15-16(21-22) p2.1-p2.0 seg2-seg3 h-32b 17-18(23-24) p3.1-p3.0 seg4-seg19 h-32 19-34(25-40) p4.0-p4.7 p5.0-p5.7 com0-com7 i/o lcd common signal output h-32 38-31 (2-1,42-37) p6.3-p6.0 p5.7-p5.4 note: parentheses indicate pin number for 42-sdip-600 package.
product overview s3c9228/p9228 1- 8 pin circuit diagrams reset v dd pull-up resistor noise filter figure 1-4. pin circuit type b v dd output output disable data v ss figure 1-5. pin circuit type c
s3c9228/p9228 product overview 1- 9 v dd pull-up enable v dd i/o pull-up resistor output disable data external interrupt input open-drain figure 1-7. pin circuit type e-4 v dd i/o pull-up resistor circuit type e to adc data aden adselect open-drain en data output disable pull-up enable figure 1-8. pin circuit type f-16a
product overview s3c9228/p9228 1- 10 out seg/com v lc3 output disable v lc2 v lc1 v ss v lc4 v lc5 figure 1-9. pin circuit type h-23
s3c9228/p9228 product overview 1- 11 v dd pull-up enable v dd i/o pull-up resistor data open-drain en circuit type h-23 lcd out en com/seg output disable figure 1-10. pin circuit type h-32 v dd pull-up enable v dd i/o pull-up resistor data open-drain en circuit type h-23 lcd out en com/seg output disable figure 1-11. pin circuit type h-32a
product overview s3c9228/p9228 1- 12 v dd pull-up enable v dd i/o pull-up resistor data open-drain en circuit type h-23 lcd out en com/seg output disable port enable (lmod.5) figure 1-12. pin circuit type h-32b
s3c9228/p9228 address spaces 2- 1 2 address spaces overview the s3c9228/p9228 microcontroller has three kinds of address space: ? program memory (rom) ? internal register file ? lcd display register file a 16 -bit address bus supports program memory operations. special instructions and related internal logic determine when the 1 6 -bit bus carries addresses for program memory. a separate 8 -bit register bus carries addresses and data between the cpu and the internal register file. the s3c9228 has 8k bytes of mask-programmable program memory on-chip . the s3c9228/p9228 microcontroller has 244 bytes general-purpose registers in its internal register file and the 20 bytes for lcd display memory is implemented in the internal register file too. fifty-six bytes in the register file are mapped for system and peripheral control functions.
address spaces s3c9228/p9228 2- 2 program memory (rom) program memory (rom) stores program code or table data. the s3c9228 has 8k bytes of mask- programable program memory. the program memory address range is therefore 0h-1fffh. the first 2 bytes of the rom (0000h? 0001h) are an interrupt vector address. the program reset address in the rom is 0100h. 8,192 256 1fffh 0100h 0 8k bytes internal program memory area interrupt vector 1 2 0002h 0001h program start 0000h (decimal) (hex) figure 2- 1. s3c9228/p9228 program memory address space
s3c9228/p9228 address spaces 2- 3 register architecture the upper 72 bytes of the s3c9228/p9228 's internal register file are addressed as working registers, system cont r ol registe r s and periphe r al control registers. the lower 184 bytes of internal register file (00h? b7 h) is called the general purpose register space . for many sam88rcri microcontrollers, the addressable area of the internal register file is further expanded by the additional of one or more register pages at general purpose register space (00h?bfh). this register file expansion is implemented by page 1 in the s3c9228/p9228 . the page 1 ( 20 8 b its ) is for lcd display register and can be used as general-purpose registers. ffh b8h ~ b7h 00h 184 bytes 72 bytes of common area d0h cfh e0h dfh working registers system control registers peripheral control registers general purpose register file and stack area (page 0) 3fh 00h lcd display registers (page 1) peripheral control registers c0h bfh general purpose register file 13h 64 bytes figure 2- 2 . internal register file organization
address spaces s3c9228/p9228 2- 4 common working register area (c0h?cfh) the sam88rcr i register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time. this16-byte address range is called common area. that is, locations in this area can be used as working registers by operations that address any location on any page in the register file. typically, these working registers serve as temporary buffers for data operations between different pages. the register (r) addressing mode can be used to access this area registers are addressed either as a single 8-bit register or as a paired 16-bit register. in 16-bit register pairs, the address of the first 8-bit register is always an even number and the address of the next register is an odd number. the most significant byte of the 16-bit data is always stored in the even-numbered register; the least significant byte is always stored in the next (+ 1) odd-numbered register. msb rn lsb rn + 1 n = even address figure 2- 3 . 16-bit register pairs + + programming tip ? addressing the common working register area as the following examples show, you should access working registers in the common area, locations c0h?cfh, using working register addressing mode only. example s: 1. ld 0c2h,40h ; invalid addressing mode! use working register addressing instead: ld r2,40h ; r2 (c2h) ? the value in location 40h 2. add 0c3h,#45h ; invalid addressing mode! use working register addressing instead: add r3,#45h ; r3 (c3h) ? r3 + 45h
s3c9228/p9228 address spaces 2- 5 system stack s 3c9 -series microcontrollers use the system stack for subroutine calls and returns and to store data. the push and pop instructions are used to control system stack operations. the s3c9228/p9228 architecture supports stack operations in the internal register file. stack operations return addresses for procedure calls and interrupts and data are stored on the stack. the contents of the pc are saved to stack by a call instruction and restored by the ret instruction. when an interrupt occurs, the contents of the pc and the flags register are pushed to the stack. the iret instruction then pops these values back to their original locations. the stack address is always decremented before a push operation and incremented after a pop operation. the stack pointer (sp) always points to the stack frame stored on the top of the stack, as shown in figure 2-4 . stack contents after a call instruction stack contents after an interrupt top of stack flags pch pcl pcl pch top of stack low address high address figure 2- 4 . stack operations stack pointer (sp) register location d9h contains the 8-bit stack pointer (sp) that is used for system stack operations. after a reset, the sp value is undetermined. because only internal memory space is implemented in the s3c9228/p9228 , the sp must be initialized to an 8- bit value in the range 00h? b7 h. note in case a stack pointer is initialized to 00h, it is decrea s ed to ffh when stack operation starts. this means that a stack pointer access invalid stack area.
address spaces s3c9228/p9228 2- 6 + + programming tip ? standard stack operations using push and pop the following example shows you how to perform stack operations in the internal register file using push and pop instructions: ld sp,#0 b8 h ; sp ? b8 h (normally, the sp is set to 0 b8 h by the ; initialization routine) ? ? ? push sym ; stack address 0b 7 h ? sym push wt con ; stack address 0b 6 h ? wt con push 20h ; stac k address 0b 5 h ? 20h push r3 ; stack address 0b 4 h ? r3 ? ? ? pop r3 ; r3 ? stack address 0b 4 h pop 20h ; 20h ? stack address 0b 5 h pop wt con ; wt con ? stack address 0b 6 h pop sym ; sym ? stack address 0b 7 h
s3c9228/p9228 addressing modes 3- 1 3 addressing modes overview instructions that are stored in program memory are fetched for execution using the program counter. instructions indicate the operation to be performed and the data to be operated on. addressing mode is the method used to determine the location of the data operand. the operands specified in sam88rc r i instructions may be condition codes, immediate data, or a location in the register file, program memory, or data memory. the sam88rcri instruction set supports six explicit addressing modes. not all of these addressing modes are available for each instruction. the addressing modes and their symbols are as follows: ? register (r) ? indirect register (ir) ? indexed (x) ? direct addr ess (da) ? relative address (ra) ? immediate (im)
addressing modes s3c9228/p9228 3- 2 register addressing mode (r) in register addressing mode, the operand is the content of a specified register (see figure 3- 1). working register addressing differs from register a ddressing because it uses a 16- byte working register s pace in the register file and a 4-bit register within that space (see figure 3- 2). dst value used in instruction execution opcode operand 8-bit register file address point to one rigister in register file one-operand instruction (example) sample instruction: dec cntr ; where cntr is the label of an 8-bit register address program memory register file figure 3- 1 . register addressing dst opcode 4-bit working register point to the woking register (1 of 16) two-operand instruction (example) sample instruction: add r1, r2 ; where r1 = c1h and r2 = c2h program memory register file src 4 lsbs operand cfh c0h . . . . figure 3- 2 . working register addressing
s3c9228/p9228 addressing modes 3- 3 indirect register addressing mode (ir) in indirect register (ir) addressing mode, the content of the specified register or register pair is the address of the operand. depending on the instruction used, the actual address may point to a register in the register file, to program memory (rom), or to an external memory space (see figures 3- 3 through 3- 6). you can use any 8-bit register to indirectly address another register. any 16-bit register pair can be used to indirectly address another memory location. 8-bit register file address one-operand instruction (example) dst address of operand used by instruction opcode address point to one rigister in register file sample instruction: rl @shift ; where shift is the label of an 8-bit register address program memory register file value used in instruction execution operand figure 3- 3 . indirect register addressing to register file
addressing modes s3c9228/p9228 3- 4 indirect register addressing mode ( c ontinued ) dst opcode pair points to rigister pair example instruction references program memory sample instructions: call @rr2 jp @rr2 program memory register file value used in instruction operand register program memory 16-bit address points to program memory figure 3- 4 . indirect register addressing to program memory
s3c9228/p9228 addressing modes 3- 5 indirect register addressing mode (c ontinued ) dst opcode operand 4-bit working register address point to the woking register (1 of 16) sample instruction: or r6, @r2 program memory register file src 4 lsbs value used in instruction operand cfh c0h . . . . figure 3- 5 . indirect working register addressing to register file
addressing modes s3c9228/p9228 3- 6 indirect register addressing mode (c oncluded ) dst opcode 4-bit working register address sample instructions: lcd r5,@rr6 ; program memory access lde r3,@rr14 ; external data memory access lde @rr4, r8 ; external data memory access program memory register file src value used in instruction operand example instruction references either program memory or data memory program memory or data memory next 3 bits point to working register pair (1 of 8) lsb selects register pair 16-bit address points to program memory or data memory cfh . . . . c0h figure 3- 6 . indirect working register addressing to program or data memory
s3c9228/p9228 addressing modes 3- 7 indexed addressing mode (x) indexed (x) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see figure 3- 7). you can use indexed addressing mode to access locations in the internal register file or in external memory. in short offset indexed addressing mode, the 8- bit displacement is treated as a signed integer in the range of ?128 to +127. this applies to external memory accesses only (see figure 3- 8). for register file addressing, an 8-b it base address provided by the instruction is added to an 8-bit offset contained in a working register. for external memory accesses, the base address is stored in the working register pair designated in the instruction. the 8-bit or 16-bit offset given in the instruction is then added to the base address (see figure 3- 9). the only instruction that supports indexed addressing mode for the internal register file is the load instruction (ld). the ldc and lde instructions support indexed addressing mode for internal program memory, external program memory, and for external data memory, when implemented. dst opcode two-operand instruction example point to one of the woking register (1 of 16) sample instruction: ld r0, #base[r1] ; where base is an 8-bit immediate value program memory register file 4 lsbs value used in instruction operand index base address ~ ~ ~ ~ + src figure 3- 7 . indexed addressing to register file
addressing modes s3c9228/p9228 3- 8 indexed addressing mode (c ontinued ) point to working register pair (1 of 8) lsb selects 16-bit address added to offset dst opcode program memory xs (offset) 4-bit working register address sample instructions: ldc r4, #04h[rr2] ; the values in the program address (rr2 + #04h) are loaded into register r4. lde r4,#04h[rr2] ; identical operation to ldc example, except that external program memory is accessed. next 3 bits register pair src 8-bits 16-bits + program memory or data memory operand value used in instruction 16-bits register file figure 3- 8 . indexed addressing to program or data memory with short offset
s3c9228/p9228 addressing modes 3- 9 indexed addressing mode (c oncluded ) point to working register pair (1 of 8) lsb selects 16-bit address added to offset program memory 4-bit working register address sample instructions: ldc r4, #1000h[rr2] ; the values in the program address (rr2 + #1000h) are loaded into register r4. lde r4, #1000h[rr2] ; identical operation to ldc example, except that external program memory is accessed. next 3 bits register pair 8-bits 16-bits + program memory or data memory operand value used in instruction 16-bits register file opcode xl h (offset) xl l (offset) dst src figure 3- 9 . indexed addressing to program or data memory with long offset
addressing modes s3c9228/p9228 3- 10 direct address mode (da) in direct address (da) mode, the instruction provides the operand's 16-bit memory address. jump (jp) and call (call) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the pc whenever a jp or call instruction is executed. the ldc and lde instructions can use direct address mode to specify the source or destination address for load operations to program memory (ldc) or to external data memory (lde), if implemented. sample instructions: ldc r5,1234h ; the values in the program address (1234h) are loaded into register r5. lde r5,1234h ; identical operation to ldc example, except that external program memory is accessed. dst/src opcode program memory "0" or "1" lower address byte lsb selects program memory or data memory: "0" = program memory "1" = data memory memory address used upper address byte program or data memory figure 3- 10 . direct addressing for load instructions
s3c9228/p9228 addressing modes 3- 11 direct address mode (c ontinued ) opcode program memory upper address byte program memory address used lower address byte sample instructions: jp c,job1 ; where job1 is a 16-bit immediate address call display ; where display is a 16-bit immediate address next opcode figure 3- 11 . direct addressing for call and jump instructions
addressing modes s3c9228/p9228 3- 12 relative address mode (ra) in relative address (ra) mode, a two's-complement signed displacement between ? 128 and + 127 is specified in the instruction. the displacement value is then added to the current pc value. the result is the address of the next instruction to be executed. before this addition occurs, the pc contains the address of the instruction immediately following the current instruction. the instructions that support ra addressing is jr. opcode program memory displacement program memory address used sample instructions: jr ult,$ + offset ; where offset is a value in the range + 127 to - 128 next opcode + signed displacement value current instruction current pc value figure 3- 12 . relative addressing immediate mode (im) in immediate (im) addressing mode, the operand value used in the instruction is the value supplied in the operand field itself. immediate addressing mode is useful for loading constant values into registers. (the operand value is in the instruction) opcode sample instruction: ld r0,#0aah program memory operand figure 3- 13 . immediate addressing
s3c9228/p9228 control registers 4- 1 4 control registers overview in this section, detailed descriptions of the s3c9228/p9228 control registers are presented in an easy-to-read format. these descriptions will help familiarize you with the mapped locations in the register file. you can also use them as a quick-reference source when writing application programs. system and peripheral registers are summarized in table 4- 1. figure 4- 1 illustrates the important features of the standard register description format. control register descriptions are arranged in alphabetical order according to register mnemonic. more information about control registers is presented in the context of the various peripheral hardware descriptions in part ii of this manual.
control registers s3c9228/p9228 4- 2 table 4-1. sys tem and peripheral c ontrol registers (page 0) register name mnemonic address (page 0) r/w decimal hex port 0 control register p0con 235 ebh r/w port 0 pull-up resistor enable register p0pur 236 ech r/w port 0 interrupt control register p0int 237 edh r/w port 0 interrupt edge selection register p0edge 238 eeh r/w port 1 control register p1con 239 efh r/w port 1 pull-up resistor enable register p1pur 240 f0h r/w port 1 interrupt control register p1int 241 f1h r/w port 1 interrupt edge selection register p1edge 242 f2h r/w port 2 control register p2con 243 f3h r/w port 2 pull-up resistor enable register p2pur 244 f4h r/w port 3 control register p3con 245 f5h r/w port 3 pull-up resistor enable register p3pur 246 f6h r/w port 3 interrupt control register p3int 247 f7h r/w port 3 interrupt edge selection register p3edge 248 f8h r/w port 4 control register (high byte) p4conh 249 f9h r/w port 4 control register (low byte) p4conl 250 fah r/w port 5 control register (high byte) p5conh 251 fbh r/w port 5 control register (low byte) p5conl 252 fch r/w port 6 control register p6con 253 fdh r/w lcd mode register lmod 254 feh r/w location ffh is not mapped.
s3c9228/p9228 control registers 4- 3 table 4- 1. sys tem and peripheral c ontrol registers (page 0) register name mnemonic address (page 0) r/w decimal hex locations d8h-b9h are not mapped. timer b control register tbcon 202 bah r/w timer 1/a control register tacon 203 bbh r/w timer b data register tbdata 204 bch r/w timer a data register tadata 205 bdh r/w timer b counter tbcnt 206 beh r timer a counter tacnt 207 bfh r a/d converter control register adcon 208 d0h r/w a/d converter data register (high byte) addatah 209 d1h r/w a/d converter data register (low byte) addatal 210 d2h r/w oscillator control register osccon 211 d3h r/w system clock control register clkcon 212 d4h r/w system flags register flags 213 d5h r/w interrupt pending register 1 intpnd1 214 d6h r/w interrupt pending register 2 intpnd2 215 d7h r/w lcd port control register lpot 216 d8h r/w stack pointer sp 217 d9h r/w watch timer control register wtcon 218 dah r/w location dbh is not mapped. basic timer control register btcon 220 dch r/w basic timer counter btcnt 221 ddh r location deh is not mapped. system mode register sym 223 dfh r/w stop control register stpcon 224 e0h r/w sio control register siocon 225 e1h r/w sio data register siodata 226 e2h r/w sio prescaler register siops 227 e3h r/w port 0 data register p0 228 e4h r/w port 1 data register p1 229 e5h r/w port 2 data register p2 230 e6h r/w port 3 data register p3 231 e7h r/w port 4 data register p4 232 e8h r/w port 5 data register p5 233 e9h r/w port 6 data register p6 234 eah r/w
control registers s3c9228/p9228 4- 4 flags - system flags register .7 .6 .5 bit identifier reset reset value read/write r = read-only w = write-only r/w = read/write ' - ' = not used bit number: msb = bit 7 lsb = bit 0 addressing mode or modes you can use to modify register values description of the effect of specific bit settings reset value notation: '-' = not used 'x' = undetermind value '0' = logic zero '1' = logic one bit number(s) that is/are appended to the register name for bit addressing d5h register address (hexadecimal) full register name register mnemonic name of individual bit or bit function .7 .6 .5 .4 .2 .3 .1 .0 x r/w x r/w x r/w x r/w 0 r/w x r/w 0 r/w x r/w carry flag (c) 0 operation dose not generate a carry or borrow condition 1 operation generates carry-out or borrow into high-order bit7 zero flag 0 operation result is a non-zero value 1 operation result is zero sign flag 0 operation generates positive number (msb = "0") 1 operation generates negative number (msb = "1") figure 4-1. register description format
s3c9228/p9228 control registers 4- 5 ad c on ? a/d converter co ntrol register d 0 h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? 0 0 0 0 0 0 read/write ? ? r/w r/w r r/w r/w r/w .7-.6 not used for the s3c9228/p9228 .5- . 4 a/d input pin selection bits 0 0 ad0 (p1.0) 0 1 ad1 (p1.1) 1 0 ad2 (p1.2) 1 1 ad3 (p1.3) .3 end of conversion bit (read-only) 0 conversion not complete 1 conversion complete .2-.1 clock source selection bits 0 0 fxx/16 0 1 fxx/8 1 0 fxx/4 1 1 fxx .0 start or enable bit 0 disable operation 1 start operation (automatically disable operation after conversion complete)
control registers s3c9228/p9228 4- 6 btc on ? basic timer co ntrol register dch bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7- .4 watchdog timer en able bits 1 0 1 0 disable watchdog function any other value enable watchdog function .3- .2 basic timer input clock selection bits 0 0 f xx /4096 0 1 f xx /1024 1 0 f xx /128 1 1 fxx/16 .1 basic timer counter clear bit ( 1) 0 no effect 1 clear the basic timer counter value (btcnt) .0 clock frequency divider clear bit for basic timer and timer/counters (2) 0 no effect 1 clear clock frequency dividers note s 1. when "1" is written to btcon. 1 , the basic timer counter value is cleared to "00h" . immediately following the write operation, the btcon.1 value is automatically cleared to "0". 2. when "1" is written to btcon. 0 , the corresponding frequency divider is cleared to "00h". immediately following the write operation, the btcon.0 value is automatically cleared to "0".
s3c9228/p9228 control registers 4- 7 clkcon ? system clock control register d4h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 oscillator irq wake-up function bit 0 enable irq for main or sub oscillator wake-up in power down mode 1 disable irq for main or sub oscillator wake-up in power down mode . 6-.5 bits 6-5 0 always logic zero .4- .3 cpu clock (system clock) selection bits 0 0 divide by 16 ( fxx /16) 0 1 divide by 8 ( fxx /8) 1 0 divide by 2 ( fxx /2) 1 1 non-divided clock ( fxx ) . 2-.0 bits 2-0 0 always logic zero
control registers s3c9228/p9228 4- 8 flags ? system flags register d5h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value x x x x ? ? ? ? read/write r/w r/w r/w r/w ? ? ? ? .7 carry flag (c) 0 operation does not generate a carry or borrow condition .6 zero flag (z) 0 operation result is a non-zero value 1 operation result is zero .5 sign flag (s) 0 operation generates a positive number (msb = "0") 1 operation generates a negative number (msb = "1") .4 overflow flag (v) 0 operation result is +127 or 3 ?128 1 operation result is 3 +127 or ?128 .3 -.0 not used for s3c9228/p9228
s3c9228/p9228 control registers 4- 9 intpnd1 ? interrupt pending register 1 d6 h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 p1.3's interrupt pending bit 0 no interrupt pending (when read), clear pending bit (when write) 1 interrupt is pending (when read) .6 p1.2's interrupt pending bit 0 no interrupt pending (when read), clear pending bit (when write) 1 interrupt is pending (when read) . 5 p1.1's interrupt pending bit 0 no interrupt pending (when read), clear pending bit (when write) 1 interrupt is pending (when read) . 4 p1.0's interrupt pending bit 0 no interrupt pending (when read), clear pending bit (when write) 1 interrupt is pending (when read) .3 p0.3's interrupt pending bit 0 no interrupt pending (when read), clear pending bit (when write) 1 interrupt is pending (when read) . 2 p0.2's interrupt pending bit 0 no interrupt pending (when read), clear pending bit (when write) 1 interrupt is pending (when read) . 1 p0.1's interrupt pending bit 0 no interrupt pending (when read), clear pending bit (when write) 1 interrupt is pending (when read) . 0 p0.0's interrupt pending bit 0 no interrupt pending (when read), clear pending bit (when write) 1 interrupt is pending (when read) note: refer to page 5-6 to clear any pending bits.
control registers s3c9228/p9228 4- 10 intpnd2 ? interrupt pending register 2 d7 h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? 0 0 0 0 0 0 read/write ? ? r/w r/w r/w r/w r/w r/w .7 -.6 not used for s3c9228/p9228 . 5 p3.1 (intp) interrupt pending bit 0 no interrupt pending (when read), clear pending bit (when write) 1 interrupt is pending (when read) . 4 p3.0 (intp) interrupt pending bit 0 no interrupt pending (when read), clear pending bit (when write) 1 interrupt is pending (when read) .3 watch timer interrupt pending bit 0 no interrupt pending (when read), clear pending bit (when write) 1 interrupt is pending (when read) . 2 sio interrupt pending bit 0 no interrupt pending (when read), clear pending bit (when write) 1 interrupt is pending (when read) . 1 timer b interrupt pending bit 0 no interrupt pending (when read), clear pending bit (when write) 1 interrupt is pending (when read) . 0 timer 1/a interrupt pending bit 0 no interrupt pending (when read), clear pending bit (when write) 1 interrupt is pending (when read) note: refer to page 5-6 to clear any pending bits.
s3c9228/p9228 control registers 4- 11 lmod ? lcd mode control register fe h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? 0 0 0 0 0 0 0 read/write ? r/w r/w r/w r/w r/w r/w r/w .7 not used for s3c9228/p9228 .6 com pins high impedance control bit 0 normal coms signal output 1 com pins are at high impedance .5 port3 high impedance control bit 0 normal i/o 1 high impedance input .4 lcd display control bit 0 display off (cut off the lcd voltage dividing resistors) 1 normal display on .3-.2 lcd duty and bias selection bits 0 0 1/3 duty, 1/3 bias; com0?com2/seg0?seg19 0 1 1/4 duty, 1/3 bias; com0?com3/seg0?seg19 1 0 1/8 duty, 1/4 bias; com0?com7/seg0?seg15 1 1 1/8 duty, 1/5 bias; com0?com7/seg0?seg15 .1-.0 lcd clock selection bits 0 0 fw/2 7 (256 hz when fw is 32.768 khz) 0 1 fw/2 6 (512 hz when fw is 32.768 khz) 1 0 fw/2 5 (1,024 hz when fw is 32.768 khz) 1 1 fw/2 4 (2,048 hz when fw is 32.768 khz)
control registers s3c9228/p9228 4- 12 lpot ? lcd port control register d8 h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? 0 0 0 0 0 0 0 read/write ? r/w r/w r/w r/w r/w r/w r/w .7 not used for s3c9228/p9228 .6-.4 seg4-seg19 and com0-com3 selection bit seg4-7 seg8-11 seg12-15 seg16-19/ com7-com4 com0-3 p4.0-p4.3 p4.4-p4.7 p5.0-p5.3 p5.4-p5.7 p6.0-p6.3 0 0 0 seg seg seg seg/com com 0 0 1 port seg seg seg/com com 0 1 0 port port seg seg/com com 0 1 1 port port port seg/com com 1 0 0 port port port port com 1 0 1 port port port port port .3 seg3/p3.0 selection bit 0 seg port 1 normal i/o port .2 seg2/p3.1 selection bit 0 seg port 1 normal i/o port .1 seg1/p2.0 selection bit 0 seg port 1 normal i/o port .0 seg0/p2.1 selection bit 0 seg port 1 normal i/o port note: seg16-seg19 are shared with com4-com7.
s3c9228/p9228 control registers 4- 13 osccon ? oscillator control register d3 h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? ? ? 0 0 ? 0 read/write ? ? ? ? r/w r/w ? r/w .7 -.4 not used for s3c9228/p9228 .3 main oscillator control bit 0 main oscillator run 1 main oscillator stop .2 sub oscillator control bit 0 sub oscillator run 1 sub oscillator stop .1 not used for s3c9228/p9228 .0 system clock selection bit 0 select main oscillator for system clock 1 select sub oscillator for system clock
control registers s3c9228/p9228 4- 14 p0con ? port 0 control register ebh bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7-.6 p0.3/buz/int configuration bits 0 0 schmitt trigger input 0 1 push-pull output 1 0 n-channel open-drain output 1 1 alternative function (buz output) .5-.4 p0.2/int configuration bits 0 0 schmitt trigger input 0 1 push-pull output 1 0 n-channel open-drain output 1 1 not available .3-.2 p0.1/t1clk/int configuration bits 0 0 schmitt trigger input (t1clk input) 0 1 push-pull output 1 0 n-channel open-drain output 1 1 not available .1-.0 p0.0/taout/int configuration bits 0 0 schmitt trigger input 0 1 push-pull output 1 0 n-channel open-drain output 1 1 alternative function (taout output)
s3c9228/p9228 control registers 4- 15 p0int ?port 0 interrupt enable register edh bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? ? ? 0 0 0 0 read/write ? ? ? ? r/w r/w r/w r/w .7-.4 not used for s3c9228/p9228 .3 p0.3's interrupt enable bit 0 disable interrupt 1 enable interrupt .2 p0.2's interrupt enable bit 0 disable interrupt 1 enable interrupt .1 p0.1's interrupt enable bit 0 disable interrupt 1 enable interrupt .0 p0.0's interrupt enable bit 0 disable interrupt 1 enable interrupt
control registers s3c9228/p9228 4- 16 p0pur ?port 0 pull-up resistors enable register ech bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? ? ? 0 0 0 0 read/write ? ? ? ? r/w r/w r/w r/w .7-.4 not used for s3c9228/p9228 .3 p0.3's pull-up resistor enable bit 0 disable pull-up resistor 1 enable pull-up resistor .2 p0.2's pull-up resistor enable bit 0 disable pull-up resistor 1 enable pull-up resistor .1 p0.1's pull-up resistor enable bit 0 disable pull-up resistor 1 enable pull-up resistor .0 p0.0's pull-up resistor enable bit 0 disable pull-up resistor 1 enable pull-up resistor
s3c9228/p9228 control registers 4- 17 p0edge ?port 0 interrupt edge selection register eeh bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? ? ? 0 0 0 0 read/write ? ? ? ? r/w r/w r/w r/w .7-.4 not used for s3c9228/p9228 .3 p0.3's interrupt edge setting bit 0 falling edge interrupt 1 rising edge interrupt .2 p0.2's interrupt state setting bit 0 falling edge interrupt 1 rising edge interrupt .1 p0.1's interrupt state setting bit 0 falling edge interrupt 1 rising edge interrupt .0 p0.0's interrupt state setting bit 0 falling edge interrupt 1 rising edge interrupt
control registers s3c9228/p9228 4- 18 p1con ? port 1 control register efh bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7-.6 p1.3/ad3/int configuration bits 0 0 schmitt trigger input 0 1 push-pull output 1 0 n-channel open-drain output 1 1 alternative function (adc mode) .5-.4 p1.2/ad2/int configuration bits 0 0 schmitt trigger input 0 1 push-pull output 1 0 n-channel open-drain output 1 1 alternative function (adc mode) .3-.2 p1.1/ad1/int configuration bits 0 0 schmitt trigger input 0 1 push-pull output 1 0 n-channel open-drain output 1 1 alternative function (adc mode) .1-.0 p1.0/ad0/int configuration bits 0 0 schmitt trigger input 0 1 push-pull output 1 0 n-channel open-drain output 1 1 alternative function (adc mode)
s3c9228/p9228 control registers 4- 19 p1int ?port 1 interrupt enable register f1h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? ? ? 0 0 0 0 read/write ? ? ? ? r/w r/w r/w r/w .7-.4 not used for s3c9228/p9228 .3 p1.3's interrupt enable bit 0 disable interrupt 1 enable interrupt .2 p1.2's interrupt enable bit 0 disable interrupt 1 enable interrupt .1 p1.1's interrupt enable bit 0 disable interrupt 1 enable interrupt .0 p1.0's interrupt enable bit 0 disable interrupt 1 enable interrupt
control registers s3c9228/p9228 4- 20 p1pur ?port 1 pull-up resistors enable register f0h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? ? ? 0 0 0 0 read/write ? ? ? ? r/w r/w r/w r/w .7-.4 not used for s3c9228/p9228 .3 p1.3's pull-up resistor enable bit 0 disable pull-up resistor 1 enable pull-up resistor .2 p1.2's pull-up resistor enable bit 0 disable pull-up resistor 1 enable pull-up resistor .1 p1.1's pull-up resistor enable bit 0 disable pull-up resistor 1 enable pull-up resistor .0 p1.0's pull-up resistor enable bit 0 disable pull-up resistor 1 enable pull-up resistor
s3c9228/p9228 control registers 4- 21 p1edge ?port 1 interrupt edge selection register f2h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? ? ? 0 0 0 0 read/write ? ? ? ? r/w r/w r/w r/w .7-.4 not used for s3c9228/p9228 .3 p1.3's interrupt edge setting bit 0 falling edge interrupt 1 rising edge interrupt .2 p1.2's interrupt state setting bit 0 falling edge interrupt 1 rising edge interrupt .1 p1.1's interrupt state setting bit 0 falling edge interrupt 1 rising edge interrupt .0 p1.0's interrupt state setting bit 0 falling edge interrupt 1 rising edge interrupt
control registers s3c9228/p9228 4- 22 p2con ? port 2 control register f3h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7-.6 p2.3 configuration bits 0 0 schmitt trigger input 0 1 push-pull output 1 0 n-channel open-drain output 1 1 not available .5-.4 p2.2/si configuration bits 0 0 schmitt trigger input (si) 0 1 push-pull output 1 0 n-channel open-drain output 1 1 not available .3-.2 p2.1/so configuration bits 0 0 schmitt trigger input 0 1 push-pull output 1 0 n-channel open-drain output 1 1 alternative function (so out) .1-.0 p2.0/sck configuration bits 0 0 schmitt trigger input (sck in) 0 1 push-pull output 1 0 n-channel open-drain output 1 1 alternative function (sck out)
s3c9228/p9228 control registers 4- 23 p2pur ?port 2 pull-up resistors enable register f4h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? ? ? 0 0 0 0 read/write ? ? ? ? r/w r/w r/w r/w .7-.4 not used for s3c9228/p9228 .3 p2.3's pull-up resistor enable bit 0 disable pull-up resistor 1 enable pull-up resistor .2 p2.2's pull-up resistor enable bit 0 disable pull-up resistor 1 enable pull-up resistor .1 p2.1's pull-up resistor enable bit 0 disable pull-up resistor 1 enable pull-up resistor .0 p2.0's pull-up resistor enable bit 0 disable pull-up resistor 1 enable pull-up resistor
control registers s3c9228/p9228 4- 24 p3con ? port 3 control register f5h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? ? ? 0 0 0 0 read/write ? ? ? ? r/w r/w r/w r/w .7-.4 not used for s3c9228/p9228 .3-.2 p3.1/seg2/intp configuration bits 0 0 schmitt trigger input 0 1 push-pull output 1 0 n-channel open-drain output 1 1 not available .1-.0 p3.0/seg3/intp configuration bits 0 0 schmitt trigger input 0 1 push-pull output 1 0 n-channel open-drain output 1 1 not available
s3c9228/p9228 control registers 4- 25 p3int ?port 3 interrupt enable register f7h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? ? ? ? ? 0 0 read/write ? ? ? ? ? ? r/w r/w .7-.2 not used for s3c9228/p9228 .1 p3.1's interrupt enable bit 0 disable interrupt 1 enable interrupt .0 p3.0's interrupt enable bit 0 disable interrupt 1 enable interrupt
control registers s3c9228/p9228 4- 26 p3pur ?port 3 pull-up resistors enable register f6h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? ? ? ? ? 0 0 read/write ? ? ? ? ? ? r/w r/w .7-.2 not used for s3c9228/p9228 .1 p3.1's pull-up resistor enable bit 0 disable pull-up resistor 1 enable pull-up resistor .0 p3.0's pull-up resistor enable bit 0 disable pull-up resistor 1 enable pull-up resistor
s3c9228/p9228 control registers 4- 27 p3edge ?port 3 interrupt edge selection register f8h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? ? ? ? ? 0 0 read/write ? ? ? ? ? ? r/w r/w .7-.4 not used for s3c9228/p9228 .1 p3.1's interrupt state setting bit 0 falling edge interrupt 1 rising edge interrupt .0 p3.0's interrupt state setting bit 0 falling edge interrupt 1 rising edge interrupt
control registers s3c9228/p9228 4- 28 p4conh ? port 4 control register high byte f9h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7-.6 p4.7/seg11 configuration bits 0 0 input mode 0 1 push-pull output 1 0 n-channel open-drain output 1 1 input, pull-up mode .5-.4 p4.6/seg10 configuration bits 0 0 input mode 0 1 push-pull output 1 0 n-channel open-drain output 1 1 input, pull-up mode .3-.2 p4.5/seg9 configuration bits 0 0 input mode 0 1 push-pull output 1 0 n-channel open-drain output 1 1 input, pull-up mode .1-.0 p4.4/seg8 configuration bits 0 0 input mode 0 1 push-pull output 1 0 n-channel open-drain output 1 1 input, pull-up mode
s3c9228/p9228 control registers 4- 29 p4conl ?port 4 control register low byte fah bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7-.6 p4.3/seg7 configuration bits 0 0 input mode 0 1 push-pull output 1 0 n-channel open-drain output 1 1 input, pull-up mode .5-.4 p4.2/seg6 configuration bits 0 0 input mode 0 1 push-pull output 1 0 n-channel open-drain output 1 1 input, pull-up mode .3-.2 p4.1/seg5 configuration bits 0 0 input mode 0 1 push-pull output 1 0 n-channel open-drain output 1 1 input, pull-up mode .1-.0 p4.0/seg4 configuration bits 0 0 input mode 0 1 push-pull output 1 0 n-channel open-drain output 1 1 input, pull-up mode
control registers s3c9228/p9228 4- 30 p5conh ? port 5 control register high byte fbh bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 -.6 p5.7/seg19/com4 configuration bits 0 0 input mode 0 1 push-pull output 1 0 n-channel open-drain output 1 1 input, pull-up mode .5-.4 p5.6/seg18/com5 configuration bits 0 0 input mode 0 1 push-pull output 1 0 n-channel open-drain output 1 1 input, pull-up mode .3-.2 p5.5/seg17/com6 configuration bits 0 0 input mode 0 1 push-pull output 1 0 n-channel open-drain output 1 1 input, pull-up mode .1-.0 p5.4/seg16/com7 configuration bits 0 0 input mode 0 1 push-pull output 1 0 n-channel open-drain output 1 1 input, pull-up mode
s3c9228/p9228 control registers 4- 31 p5conl ? port 5 control register low byte fch bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 -.6 p5.3/seg15 configuration bits 0 0 input mode 0 1 push-pull output 1 0 n-channel open-drain output 1 1 input, pull-up mode .5-.4 p5.2/seg14 configuration bits 0 0 input mode 0 1 push-pull output 1 0 n-channel open-drain output 1 1 input, pull-up mode .3-.2 p5.1/seg13 configuration bits 0 0 input mode 0 1 push-pull output 1 0 n-channel open-drain output 1 1 input, pull-up mode .1-.0 p5.0/seg12 configuration bits 0 0 input mode 0 1 push-pull output 1 0 n-channel open-drain output 1 1 input, pull-up mode
control registers s3c9228/p9228 4- 32 p6con ? port 6 control register high byte fdh bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 -.6 p6.3/com0 configuration bits 0 0 input mode 0 1 push-pull output 1 0 n-channel open-drain output 1 1 input, pull-up mode .5-.4 p6.2/com1 configuration bits 0 0 input mode 0 1 push-pull output 1 0 n-channel open-drain output 1 1 input, pull-up mode .3-.2 p6.1/com2 configuration bits 0 0 input mode 0 1 push-pull output 1 0 n-channel open-drain output 1 1 input, pull-up mode .1-.0 p6.0/com3 configuration bits 0 0 input mode 0 1 push-pull output 1 0 n-channel open-drain output 1 1 input, pull-up mode
s3c9228/p9228 control registers 4- 33 siocon ? sio control register e1 h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 ? read/write r/w r/w r/w r/w r/w r/w r/w ? .7 sio shift clock selection bit 0 internal clock ( p.s clock) 1 external clock (sck) .6 data direction control bit 0 msb-first mode 1 lsb-first mode . 5 sio mode selection bit 0 receive-only mode 1 transmit/receive mode . 4 shift clock edge selection bit 0 tx at falling edges, rx at rising edges 1 tx at rising edges, rx at falling edges .3 sio counter clear and shift start bit 0 no action 1 clear 3-bit counter and start shifting . 2 sio shift operation enable bit 0 disable shifter and clock counter 1 enable shifter and clock counter . 1 sio interrupt enable bit 0 disable sio interrupt 1 enable sio interrupt . 0 not used for s3c9228/p9228
control registers s3c9228/p9228 4- 34 stpcon ? stop control register e0h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 stop control bits 1 0 1 0 0 1 0 1 enable stop instruction other values disable stop instruction note: before executing the stop instruction, the stpcon register must be set to "10100101b". otherwise the stop instruction will not execute.
s3c9228/p9228 control registers 4- 35 sym ? system mode register dfh bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? ? ? 0 0 0 0 read/write ? ? ? ? r/w r/w r/w r/w .7-.4 not used for s3c9228/p9228 .3 global interrupt enable bit 0 g lobal interrupt processing disable (di instruction) 1 g lobal interrupt processing enable (ei instruction) .2- .0 page selection bits 0 0 0 page 0 0 0 1 page 1 other values not available
control registers s3c9228/p9228 4- 36 t a con ? timer 1/a control register bb h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 ? read/write r/w r/w r/w r/w r/w r/w r/w ? .7 timer 1 mode selection bit 0 two 8-bit timers mode (timer a/b) 1 one 16-bit timer mode (timer 1) .6-.4 timer 1/a clock selection bits 0 0 0 fxx/512 0 0 1 fxx/256 0 1 0 fxx/64 0 1 1 fxx/8 1 0 0 fxx (system clock) 1 0 1 fxt (sub clock) 1 1 0 t1clk (external clock) 1 1 1 not available .3 timer 1/a counter clear bit 0 no effect 1 clear the timer 1/a counter (when write) .2 timer 1/a counter enable bit 0 disable counting operation 1 enable counting operation .1 timer 1/a interrupt enable bit 0 disable interrupt 1 enable interrupt .0 bit 0 not used for s3c9228/p9228
s3c9228/p9228 control registers 4- 37 t b con ? timer b control register ba h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? 0 0 0 0 0 0 ? read/write ? r/w r/w r/w r/w r/w r/w ? .7 not used for s3c9228/p9228 .6-.4 timer b clock selection bits 0 0 0 fxx/512 0 0 1 fxx/256 0 1 0 fxx/64 0 1 1 fxx/8 1 0 0 fxx (system clock) 1 0 1 fxt (sub clock) .3 timer b counter clear bit 0 no effect 1 clear the timer b counter (when write) .2 timer b counter enable bit 0 disable counting operation 1 enable counting operation .1 timer b interrupt enable bit 0 disable interrupt 1 enable interrupt .0 not used for s3c9228/p9228
control registers s3c9228/p9228 4- 38 wtcon ? watch timer control register da h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 ? read/write r/w r/w r/w r/w r/w r/w r/w ? .7 watch timer clock selection bit 0 select main clock divided by 2 7 (fx/128) 1 select sub clock ( fxt) .6 watch timer interrupt enable bit 0 disable watch timer interrupt 1 enable watch timer interrupt .5-.4 buzzer signal selection bits 0 0 0.5 khz 0 1 1 khz 1 0 2 khz 1 1 4 khz .3-.2 watch timer speed selection bits 0 0 set watch timer interrupt to 1s 0 1 set watch timer interrupt to 0.5s 1 0 set watch timer interrupt to 0.25s 1 1 set watch timer interrupt to 3.91ms .1 watch timer enable bit 0 disable watch timer; clear frequency dividing circuits 1 enable watch timer .0 not used for s3c9228/p9228
s3c9228/p9228 interrupt structure 5- 1 5 interrupt structure overview the sam88rcri interrupt structure has two basic components: a vector, and sources. the number of interrupt sources can be serviced through a interrupt vector which is assigned in rom address 0000h?0001h. sources vector s1 s2 s3 sn 0000h 0001h notes: 1. the sam88rcri interrupt has only one vector address (0000h-0001h). 2. the number of sn value is expandable. figure 5- 1 . s3c9 -series interrupt type interrupt processing control points interrupt processing can be controlled in two ways: globally, or by specific interrupt level and source. the system- level control points in the interrupt structure are therefore: ? global interrupt enable and disable (by ei and di instructions) ? interrupt source en able and disable settings in the corresponding peripheral control register(s) enable/disable interrupt instructions (ei, di) the system mode register, sym (dfh), is used to enable and disable interrupt processing. sym.3 is the enable and disable bit for global interrupt processing, which you can set by modifying sym.3 . an enable interrupt (ei) instruction must be included in the initialization routine that follows a reset operation in order to enable interrupt processing. al though you can manipulate sym.3 directly to enable and disable interrupts during normal operation, we recommend that you use the ei and di instructions for this purpose.
interrupt structure s3c9228/p9228 5- 2 interrupt pending function types when the interrupt service routine has executed, the application program's service routine must clear the appropriate pending bit before the return from interrupt subroutine (iret) occurs. interrupt priority because there is not a interrupt priority register in sam87 rc r i , the order of service is determined by a sequence of source which is executed in interrupt service routine. s r q interrupt pending register global interrupt control (ei, di instruction) vector interrupt cycle interrpt priority is determind by software polling method "ei" instruction execution reset source interrupts source interrupt enable figure 5- 2 . interrupt function diagram
s3c9228/p9228 interrupt structure 5- 3 interrupt source service sequence the interrupt request polling and servicing sequence is as follows: 1. a source generates an interrupt request by setting the interrupt request pending bit to "1". 2. the cpu generates an interrupt acknowledge signal. 3. the service routine starts and the source's pending flag is cleared to "0" by software. 4. interrupt priority must be determined by software polling method. interrupt service routines before an interrupt request can be serviced, the following conditions must be met: ? interrupt proce ssing must be enabled (ei, sym.3 = "1") ? interrupt must be enabled at the interrupt's source (peripheral control register) if all of the above conditions are met, the interrupt request is acknowledged at the end of the instruction cycle. the cpu then initiates an interrupt machine cycle that completes the following processing sequence: 1. reset (clear to "0") the global interrupt enable bit in the sym register (di, sym. 3 = "0") to disable all subsequent interrupts. 2. save the program counter and status flags to stack. 3. branch to the interrupt vector to fetch the service routine's address. 4. pass control to the interrupt service ro utine. when the interrupt service routine is completed, an interrupt return instruction (iret) occurs. the iret restores the pc and status flags and sets sym.3 to "1"(ei), allowing the cpu to process the next interrupt request. generating interrupt vector addresses the interrupt vector area in the rom contains the address of the interrupt service routine. vectored interrupt processing follows this sequence: 1. push the program counter's low-byte value to s tack. 2. push the program counter's high-byte value to stack. 3. push the flags register values to stack. 4. fetch the service routine's high-byte address from the vector address 0000h. 5. fetch the service routine's low-byte address from the vector address 0001h. 6. branch to the service routine specified by the 16-bit vector address.
interrupt structure s3c9228/p9228 5- 4 s3c9228/p9228 interrupt structure the s3c9228/p9228 microcontroller has fourteen peripheral interrupt sources: ? timer 1/a interr upt ? timer b interrupt ? sio interrupt ? watch timer interrupt ? four external interrupts for port 0 ? four external interrupts for port 1 ? two external interrupts for port 3
s3c9228/p9228 interrupt structure 5- 5 sym.3 (ei, di) p0int.0 p0.0 external interript p0int.1 p0.1 external interript p0.3 external interript p0.2 external interript p0int.2 p0int.3 intpnd1.0 intpnd1.1 intpnd1.2 intpnd1.3 p1.0 external interript p1int.0 p1.2 external interript p1.3 external interrupt p1.1 external interript p1int.1 p1int.2 p1int.3 tacon.1 tbcon.1 intpnd1.4 intpnd1.5 intpnd1.6 intpnd1.7 intpnd2.0 intpnd2.1 siocon.1 wtcon.1 p3int.0 p3int.1 intpnd2.2 intpnd2.3 intpnd2.4 intpnd2.5 0000h 0001h vector enable/disable pending sources timer b interrupt timer 1/a interrupt watch timer interrupt p3.0 interrupt sio interrupt p3.1 interrupt figure 5- 3 . s3c9228/p9228 interrupt structure
interrupt structure s3c9228/p9228 5- 6 programming tip ? how to clear an interrupt pending bit as the following examples are shown, a load instruction should be used to clear an interrupt pending bit. examples: 1. ld intpnd1, #11111011b ; clear p0.2's interrupt pending bit iret 2. l d intpnd2, #11110111b ; clear watch timer interrupt pending bit iret
s3c9228/p9228 s am8 8rc ri instruction set 6 - 1 6 sam8 8rc r i instruction set overview the sam88rcri instruction set is designed to support the large register file. it includes a full complement of 8- bit arithmetic and logic operations. there are 41 instructions. no special i/o instructions are necessary because i/o control and data registers are mapped directly into the register file. flexible instructions for bit addressing, rotate, and shift operations complete the powerful data manipulation capabilities of the sam88rcri instruction set. register addressing to access an individual register, an 8-bit address in the range 0-255 or the 4-bit address of a working register is specified. paired registers can be used to construct 1 6 -bit program memory or data memory addresses. for detailed information about register addressing, please refer to section 2, "address spaces". addressing modes there are six addressing modes: register (r), indirect register (ir), indexed (x), direct (da), relative (ra), and immediate (im). for detailed descriptions of these addressing modes, please refer to section 3, "addressing modes".
sam8 8 ri instruction set s3c9228/p9228 6 - 2 table 6- 1. instruction group summary mnemonic operands instruction load instructions clr dst clear ld dst,src load ldc dst,src load program memory lde dst,src load external data memory ldcd dst,src load program memory and decrement lded dst,src load external data memory and decrement ldci dst,src load program memory and increment ldei dst,src load external data memory and increment pop dst pop from stack push src push to stack arithmetic instructions adc dst,src add with carry add dst,src add cp dst,src compare dec dst decrement inc dst increment sbc dst,src subtract with carry sub dst,src subtract logic instructions and dst,src logical and com dst complement or dst,src logical or xor dst,src logical exclusive or
s3c9228/p9228 s am8 8rc ri instruction set 6 - 3 table 6- 1 . instruction group summary (continued) mnemonic operands instruction program control instructions call dst call procedure iret interrupt return jp cc,dst jump on condition code jp dst jump unconditional jr cc,dst jump relative on condition code ret return bit manipulation instructions tcm dst,src test complement under mask tm dst,src test under mask rotate and shift instructions rl dst rotate left rlc dst rotate left through carry rr dst rotate right rrc dst rotate right through carry sra dst shift right arithmetic cpu control instructions ccf complement carry flag di disable interrupts ei enable interrupts idle enter idle mode nop no operation rcf reset carry flag scf set carry flag stop enter stop mode
sam8 8 ri instruction set s3c9228/p9228 6 - 4 flags register (flags) the flags register contains eight bits that describe the current status of cpu operations. four of these bits, flags.4 ? flags.7, can be tested and used with conditional jump instructions; flags register can be set or reset by instructions as long as its outcome does not affect the flags, such as, load instruction. logical and arithmetic instructions such as, and, or, xor, add, and sub can affect the flags register. for example, the and instruction updates the zero, sign and overflow flags based on the outcome of the and instruction. if the and instruction uses the flags register as the destination, then simultaneously, two write will occur to the flags register producing an unpredictable result. .7 .6 .5 .4 .3 .2 .1 .0 lsb msb system flags register (flags) d5h, r/w not mapped carry flag (c) zero flag (z) sign flag (s) overflow flag (v) figure 6- 1 . system flags register (flags) flag descriptions overflow flag (flags.4, v) the v flag is set to "1" when the result of a two's-complement operation is greater than + 127 or less than ? 128. it is also cleared to "0" following logic operations. sign flag (flags.5, s) following arithmetic, logic, rotate, or shift operations, the sign bit identifies the state of the msb of the result. a logic zero indicates a positive number and a logic one indicates a negative number. zero flag (flags.6, z) for arithmetic and logic operations, the z flag is set to "1" if the result of the operation is zero. for operations that test register bits, and for shift and rotate operations, the z flag is set to "1" if the result is logic zero. carry flag (flags.7, c) the c flag is set to "1" if the result from an arithmetic operation generates a carry-out from or a borrow to the bit 7 position (msb). after rotate and shift operations, it contains the last value shifted out of the specified register. program instructions can set, clear, or complement the carry flag.
s3c9228/p9228 s am8 8rc ri instruction set 6 - 5 instruction set notation table 6- 2 . flag notation conventions flag description c carry flag z zero flag s sign flag v overflow flag 0 cleared to logic zero 1 set to logic one * set or cleared according to operation ? value is unaffected x value is undefined table 6- 3 . instruction set symbols symbol description dst destination operand src source operand @ indirect register address prefix pc program counter flags flags register (d5h) # immediate operand or register address prefix h hexadecimal number suffix d decimal number suffix b binary number suffix opc opcode
sam8 8 ri instruction set s3c9228/p9228 6 - 6 table 6- 4 . instruction notation conventions notation description actual operand range cc condition code see list of condition codes in table 6- 6. r working register only rn (n = 0?15) rr working register pair rrp (p = 0, 2, 4, ..., 14) r register or working register reg or rn ( reg = 0?255, n = 0?15) rr register pair or working register pair reg or rrp ( reg = 0?254, even number only, where p = 0, 2, ..., 14) ir indirect working register only @ rn (n = 0?15) ir indirect register or indirect working register @ rn or @ reg ( reg = 0?255, n = 0?15) irr indirect working register pair only @ rrp (p = 0, 2, ..., 14) irr indirect register pair or indirect working register pair @ rrp or @ reg ( reg = 0?254, even only, where p = 0, 2, ..., 14) x indexed addressing mode # reg[ rn] ( reg = 0?255, n = 0?15) xs indexed (short offset) addressing mode # addr[ rrp] ( addr = range ?128 to +127, where p = 0, 2, ..., 14) xl indexed (long offset) addressing mode # addr [ rrp] ( addr = range 0?8191, where p = 0, 2, ..., 14) da direct addressing mode addr ( addr = range 0?8191) ra relative addressing mode addr ( addr = number in the range +127 to ?128 that is an offset relative to the address of the next instruction) im immediate addressing mode #data (data = 0?255)
s3c9228/p9228 s am8 8rc ri instruction set 6 - 7 table 6- 5 . opcode quick reference opcode map lower nibble (hex) ? 0 1 2 3 4 5 6 7 u 0 dec r1 dec ir1 add r1,r2 add r1,ir2 add r2,r1 add ir2,r1 add r1,im p 1 rlc r1 rlc ir1 adc r1,r2 adc r1,ir2 adc r2,r1 adc ir2,r1 adc r1,im p 2 inc r1 inc ir1 sub r1,r2 sub r1,ir2 sub r2,r1 sub ir2,r1 sub r1,im e 3 jp irr1 sbc r1,r2 sbc r1,ir2 sbc r2,r1 sbc ir2,r1 sbc r1,im r 4 or r1,r2 or r1,ir2 or r2,r1 or ir2,r1 or r1,im 5 pop r1 pop ir1 and r1,r2 and r1,ir2 and r2,r1 and ir2,r1 and r1,im n 6 com r1 com ir1 tcm r1,r2 tcm r1,ir2 tcm r2,r1 tcm ir2,r1 tcm r1,im i 7 push r2 push ir2 tm r1,r2 tm r1,ir2 tm r2,r1 tm ir2,r1 tm r1,im b 8 ld r1, x, r2 b 9 rl r1 rl ir1 ld r2, x, r1 l a cp r1,r2 cp r1,ir2 cp r2,r1 cp ir2,r1 cp r1,im ldc r1, irr2, xl e b clr r1 clr ir1 xor r1,r2 xor r1,ir2 xor r2,r1 xor ir2,r1 xor r1,im ldc r2, irr2, xl c rrc r1 rrc ir1 ldc r1,irr2 ld r1, ir2 h d sra r1 sra ir1 ldc r2,irr1 ld ir1,im ld ir1, r2 e e rr r1 rr ir1 ldcd r1,irr2 ldci r1,irr2 ld r2,r1 ld r2,ir1 ld r1,im ldc r1, irr2, xs x f call irr1 ld ir2,r1 call da1 ldc r2, irr1, xs
sam8 8 ri instruction set s3c9228/p9228 6 - 8 table 6- 5 . opcode quick reference (continued) opcode map lower nibble (hex) ? 8 9 a b c d e f u 0 ld r1,r2 ld r2,r1 jr cc,ra ld r1,im jp cc,da inc r1 p 1 p 2 e 3 r 4 5 n 6 idle i 7 stop b 8 di b 9 ei l a re t e b iret c rcf h d scf e e ccf x f ld r1,r2 ld r2,r1 jr cc,ra ld r1,im jp cc,da inc r1 nop
s3c9228/p9228 s am8 8rc ri instruction set 6 - 9 condition codes the opcode of a conditional jump always contains a 4-bit field called the condition code (cc). this specifies under which conditions it is to execute the jump. for example, a conditional jump with the condition code for "equal" after a compare operation only jumps if the two operands are equal. condition codes are listed in table 6- 6. the carry (c), zero (z), sign (s), and overflow (v) flags are used to control the operation of conditional jump instructions. table 6- 6 . condition codes binary mnemonic description flags set 0000 f always false ? 1000 t always true ? 0111 (1) c carry c = 1 1111 (1) nc no carry c = 0 0110 (1) z zero z = 1 1110 (1) nz not zero z = 0 1101 pl plus s = 0 0101 mi minus s = 1 0100 ov overflow v = 1 1100 nov no overflow v = 0 0110 (1) eq equal z = 1 1110 (1) ne not equal z = 0 1001 ge greater than or equal (s xor v) = 0 0001 lt less than (s xor v) = 1 1010 gt greater than (z or (s xor v)) = 0 0010 le less than or equal (z or (s xor v)) = 1 1111 (1) uge unsigned greater than or equal c = 0 0111 (1) ult unsigned less than c = 1 1011 ugt unsigned greater than (c = 0 and z = 0) = 1 0011 ule unsigned less than or equal (c or z) = 1 notes: 1. i ndicate condition codes that are related to two different mnemonics but which test the same flag. for exa mple, z and eq are both true if the zero flag (z) is set, but after an add instruction, z would probably be used; after a cp instruction, however, eq would probably be used. 2. for operations involving unsigned numbers, the special condition codes uge, ult, ugt, and ule must be used.
sam8 8 ri instruction set s3c9228/p9228 6 - 10 instruction descriptions this section contains detailed information and programming examples for each instruction in the sam88rcri instruction set. information is arranged in a consistent format for improved readability and for fast referencing. the following information is included in each instruction description: ? instruction name (mnemonic) ? full instruction name ? source/destination format of the instruction operand ? shorthand notation of the instruction's operation ? textual description of the instruction's effect ? specific flag settings affected by the instruction ? detailed description of the instruction's format, execution time, and addressing mode(s) ? programming example(s) explaining how to use the instruction
s3c9228/p9228 s am8 8rc ri instruction set 6 - 11 adc ? add with carry adc dst,src operation: dst dst + src + c the source operand, along with the setting of the carry flag, is added to the destination operand and the sum is stored in the destination. the contents of the source are unaffected. two's- complement addition is performed. in multiple precision arithmetic, this instruction permits the carry from the addition of low-order operands to be carried into the addition of high-order operands. flags: c: set if there is a carry from the most significant bit of the result; cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurs, that is, if both operands are of the same sign and the result is of the opposite sign; cleared otherwise. d: always cleared to "0". h: set if there is a carry from the most significant bit of the low-order four bits of the result; cleared otherwise. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 12 r r 6 13 r lr opc src dst 3 6 14 r r 6 15 r ir opc dst src 3 6 16 r im examples: given: r1 = 10h, r2 = 03h, c flag = "1", register 01h = 20h, register 02h = 03h, and register 03h = 0ah: adc r1,r2 ? r1 = 14h, r2 = 03h adc r1,@r2 ? r1 = 1bh, r2 = 03h adc 01h,02h ? register 01h = 24h, register 02h = 03h adc 01h,@02h ? register 01h = 2bh, register 02h = 03h adc 01h,#11h ? register 01h = 32h in the first example, destination register r1 contains the value 10h, the carry flag is set to "1", and the source working register r2 contains the value 03h. the statement "adc r1,r2" adds 03h and the carry flag value ("1") to the destination value 10h, leaving 14h in register r1.
sam8 8 ri instruction set s3c9228/p9228 6 - 12 add ? add add dst,src operation: dst dst + src the source operand is added to the destination operand and the sum is stored in the destination. the contents of the source are unaffected. two's-complement addition is performed. flags: c: set if there is a carry from the most significant bit of the result; cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred, that is, if both operands are of the same sign and the result is of the opposite sign; cleared otherwise. d: always cleared to "0". h: set if a carry from the low-order nibble occurred. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 02 r r 6 03 r lr opc src dst 3 6 04 r r 6 05 r ir opc dst src 3 6 06 r im examples: given: r1 = 12h, r2 = 03h, register 01h = 21h, register 02h = 03h, register 03h = 0ah: add r1,r2 ? r1 = 15h, r2 = 03h add r1,@r2 ? r1 = 1ch, r2 = 03h add 01h,02h ? register 01h = 24h, register 02h = 03h add 01h,@02h ? register 01h = 2bh, register 02h = 0 3h add 01h,#25h ? register 01h = 46h in the first example, destination working register r1 contains 12h and the source working register r2 contains 03h. the statement "add r1,r2" adds 03h to 12h, leaving the value 15h in register r1.
s3c9228/p9228 s am8 8rc ri instruction set 6 - 13 and ? logical and and dst,src operation: dst dst and src the source operand is logically anded with the destination operand. the result is stored in the destination. the and operation results in a "1" bit being stored whenever the corresponding bits in the two operands are both logic ones; otherwise a "0" bit value is stored. the contents of the source are unaffected. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always cleared to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 52 r r 6 53 r lr opc src dst 3 6 54 r r 6 55 r ir opc dst src 3 6 56 r im examples: given: r1 = 12h, r2 = 03h, register 01h = 21h, register 02h = 03h, register 03h = 0ah: and r1,r2 ? r1 = 02h, r2 = 03h and r1,@r2 ? r1 = 02h, r2 = 03h and 01h,02h ? register 01h = 01h, register 02h = 03h and 01h,@02h ? register 01h = 00h, register 02h = 03h and 01h,#25h ? register 01h = 21h in the first example, destination working register r1 contains the value 12h and the source working register r2 contains 03h. the statement "and r1,r2" logically ands the source operand 03h with the destination operand value 12h, leaving the value 02h in register r1.
sam8 8 ri instruction set s3c9228/p9228 6 - 14 call ? call procedure call dst operation: sp sp ? 1 @sp pcl sp sp ?1 @sp pch pc dst the current contents of the program counter are pushed onto the top of the stack. the program counter value used is the address of the first instruction following the call instruction. the specified destination address is then loaded into the program counter and points to the first instruction of a procedure. at the end of the procedure the return instruction (ret) can be used to return to the original program flow. ret pops the top of the stack back into the program counter. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst opc dst 3 14 f6 da opc dst 2 12 f4 irr examples: given: r0 = 15h, r1 = 21h, pc = 1a47h, and sp = 0b2h: call 1521h ? sp = 0b0h (memory locations 00h = 1ah, 01h = 4ah, where 4ah is the address that follows the instruction.) call @rr0 ? sp = 0b0h (00h = 1ah, 01h = 49h) in the first example, if the program counter value is 1a47h and the stack pointer contains the value 0b2h, the statement "call 1521h" pushes the current pc value onto the top of the stack. the stack pointer now points to memory location 00h. the pc is then loaded with the value 1521h, the address of the first instruction in the program sequence to be executed. if the contents of the program counter and stack pointer are the same as in the first example, the statement "call @rr0" produces the same result except that the 49h is stored in stack location 01h (because the two-byte instruction format was used). the pc is then loaded with the value 1521h, the address of the first instruction in the program sequence to be executed.
s3c9228/p9228 s am8 8rc ri instruction set 6 - 15 ccf ? complement carry flag ccf operation: c not c the carry flag (c) is complemented. if c = "1", the value of the carry flag is changed to logic zero; if c = "0", the value of the carry flag is changed to logic one. flags: c: complemented. no other flags are affected. format: bytes cycles opcode (hex) opc 1 4 ef example: given: the carry flag = "0": ccf if the carry flag = "0", the ccf instruction complements it in the flags register (0d5h), changing its value from logic zero to logic one.
sam8 8 ri instruction set s3c9228/p9228 6 - 16 clr ? clear clr dst operation: dst "0" the destination location is cleared to "0". flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 b0 r 4 b1 ir examples: given: register 00h = 4fh, register 01h = 02h, and register 02h = 5eh: clr 00h ? register 00h = 00h clr @01h ? register 01h = 02h, register 02h = 00h in register (r) addressing mode, the statement "clr 00h" clears the destination register 00h value to 00h. in the second example, the statement "clr @01h" uses indirect register (ir) addressing mode to clear the 02h register value to 00h.
s3c9228/p9228 s am8 8rc ri instruction set 6 - 17 com ? complement com dst operation: dst not dst the contents of the destination location are complemented (one's complement); all "1s" are changed to "0s", and vice-versa. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always reset to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 60 r 4 61 ir examples: given: r1 = 07h and register 07h = 0f1h: com r1 ? r1 = 0f8h com @r1 ? r1 = 07h, register 07h = 0eh in the first example, destination working register r1 contains the value 07h (00000111b). the statement "com r1" complements all the bits in r1: all logic ones are changed to logic zeros, and vice-versa, leaving the value 0f8h (11111000b). in the second example, indirect register (ir) addressing mode is used to complement the value of destination register 07h (11110001b), leaving the new value 0eh (00001110b).
sam8 8 ri instruction set s3c9228/p9228 6 - 18 cp ? compare cp dst,src operation: dst ? src the source operand is compared to (subtracted from) the destination operand, and the appropriate flags are set accordingly. the contents of both operands are unaffected by the comparison. flags: c: set if a "borrow" occurred ( src > dst); cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the operands were of opposite signs and the sign of the result is of the same as the sign of the source operand; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 a2 r r 6 a3 r lr opc src dst 3 6 a4 r r 6 a5 r ir opc dst src 3 6 a6 r im examples: 1. given: r1 = 02h and r2 = 03h: cp r1,r2 ? set the c and s flags destination working register r1 contains the value 02h and source register r2 contains the value 03h. the statement "cp r1,r2" subtracts the r2 value (source/subtrahend) from the r1 value (destination/minuend). because a "borrow" occurs and the difference is negative, c and s are "1". 2. given: r1 = 05h and r2 = 0ah: cp r1,r2 jp uge,skip inc r1 skip ld r3,r1 in this example, destination working register r1 contains the value 05h which is less than the contents of the source working register r2 (0ah). the statement "cp r1,r2" generates c = "1" and the jp instruction does not jump to the skip location. after the statement "ld r3,r1" executes, the value 06h remains in working register r3.
s3c9228/p9228 s am8 8rc ri instruction set 6 - 19 dec ? decrement dec dst operation: dst dst ? 1 the contents of the destination operand are decremented by one. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if result is negative; cleared otherwise. v: set if arithmetic overflow occurred, that is, dst value is ?128(80h) and result value is +127(7fh); cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 00 r 4 01 ir examples: given: r1 = 03h and register 03h = 10h: dec r1 ? r1 = 02h dec @r1 ? register 03h = 0fh in the first example, if working register r1 contains the value 03h, the statement "dec r1" decrements the hexadecimal value by one, leaving the value 02h. in the second example, the statement "dec @r1" decrements the value 10h contained in the destination register 03h by one, leaving the value 0fh.
sam8 8 ri instruction set s3c9228/p9228 6 - 20 di ? disable interrupts di operation: sym (2) 0 bit zero of the system mode register, sym.2, is cleared to "0", globally disabling all interrupt processing. interrupt requests will continue to set their respective interrupt pending bits, but the cpu will not service them while interrupt processing is disabled. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 4 8f example: given: sym = 04h: di if the value of the sym register is 04h, the statement "di" leaves the new value 00h in the register and clears sym.2 to "0", disabling interrupt processing.
s3c9228/p9228 s am8 8rc ri instruction set 6 - 21 ei ? enable interrupts ei operation: sym (2) 1 an ei instruction sets bit 2 of the system mode register, sym.2 to "1". this allows interrupts to be serviced as they occur. if an interrupt's pending bit was set while interrupt processing was disabled (by executing a di instruction), it will be serviced when you execute the ei instruction. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 4 9f example: given: sym = 00h: ei if the sym register contains the value 00h, that is, if interrupts are currently disabled, the statement "ei" sets the sym register to 04h, enabling all interrupts (sym.2 is the enable bit for global interrupt processing) .
sam8 8 ri instruction set s3c9228/p9228 6 - 22 idle ? idle operation idle operation: the idle instruction stops the cpu clock while allowing system clock oscillation to continue. idle mode can be released by an interrupt request (irq) or an external reset operation. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc 1 4 6f ? ? example: the instruction idle stops the cpu clock but not the system clock.
s3c9228/p9228 s am8 8rc ri instruction set 6 - 23 inc ? increment inc dst operation: dst dst + 1 the contents of the destination operand are incremented by one. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred, that is dst value is +127(7fh) and result is ?128(80h); cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst dst | opc 1 4 re r r = 0 to f opc dst 2 4 20 r 4 21 ir examples: given: r0 = 1bh, register 00h = 0ch, and register 1bh = 0fh: inc r0 ? r0 = 1ch inc 00h ? register 00h = 0dh inc @r0 ? r0 = 1bh, register 01h = 10h in the first example, if destination working register r0 contains the value 1bh, the statement "inc r0" leaves the value 1ch in that same register. the next example shows the effect an inc instruction has on register 00h, assuming that it contains the value 0ch. in the third example, inc is used in indirect register (ir) addressing mode to increment the value of register 1bh from 0fh to 10h.
sam8 8 ri instruction set s3c9228/p9228 6 - 24 iret ? interrupt return iret iret operation: flags @sp sp sp + 1 pc @sp sp sp + 2 sym(2) 1 this instruction is used at the end of an interrupt service routine. it restores the flag register and the program counter. it also re-enables global interrupts. flags: all flags are restored to their original settings (that is, the settings before the interrupt occurred). format: iret (normal) bytes cycles opcode (hex) opc 1 6 bf
s3c9228/p9228 s am8 8rc ri instruction set 6 - 25 jp ? jump jp cc,dst (conditional) jp dst (unconditional) operation: if cc is true, pc dst the conditional jump instruction transfers program control to the destination address if the condition specified by the condition code (cc) is true; otherwise, the instruction following the jp instruction is executed. the unconditional jp simply replaces the contents of the pc with the contents of the specified register pair. control then passes to the statement addressed by the pc. flags: no flags are affected. format: (1) (2) bytes cycles opcode (hex) addr mode dst cc | opc dst 3 8 (3) ccd da cc = 0 to f opc dst 2 8 30 irr notes: 1. the 3-byte format is used for a conditional jump and the 2-byte format for an unconditional jump. 2. in the first byte of the three-byte instruction format (conditional jump), the condition code and the opcode are both four bits. examples: given: the carry flag (c) = "1", register 00 = 01h, and register 01 = 20h: jp c,label_w ? label_w = 1000h, pc = 1000h jp @00h ? pc = 0120h the first example shows a conditional jp. assuming that the carry flag is set to "1", the statement "jp c,label_w" replaces the contents of the pc with the value 1000h and transfers control to that location. had the carry flag not been set, control would then have passed to the statement immediately following the jp instruction. the second example shows an unconditional jp. the statement "jp @00" replaces the contents of the pc with the contents of the register pair 00h and 01h, leaving the value 0120h.
sam8 8 ri instruction set s3c9228/p9228 6 - 26 jr ? jump relative jr cc,dst operation: if cc is true, pc pc + dst if the condition specified by the condition code (cc) is true, the relative address is added to the program counter and control passes to the statement whose address is now in the program counter; otherwise, the instruction following the jr instruction is executed (see list of condition codes). the range of the relative address is +127, ?128, and the original value of the program counter is taken to be the address of the first instruction byte following the jr statement. flags: no flags are affected. format: (1) bytes cycles opcode (hex) addr mode dst cc | opc dst 2 6 (2) ccb ra cc = 0 to f note : in the first byte of the two-byte instruction format, the condition code and the opcode are each four bits. example: given: the carry flag = "1" and label_x = 1ff7h: jr c,label_x ? pc = 1ff7h if the carry flag is set (that is, if the condition code is true), the statement "jr c,label_x" will pass control to the statement whose address is now in the pc. otherwise, the program instruction following the jr would be executed.
s3c9228/p9228 s am8 8rc ri instruction set 6 - 27 ld ? load ld dst,src operation: dst src the contents of the source are loaded into the destination. the source's contents are unaffected. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src dst | opc src 2 4 rc r im 4 r8 r r src | opc dst 2 4 r9 r r r = 0 to f opc dst | src 2 4 c7 r lr 4 d7 ir r opc src dst 3 6 e4 r r 6 e5 r ir opc dst src 3 6 e6 r im 6 d6 ir im opc src dst 3 6 f5 ir r opc dst | src x 3 6 87 r x [r] opc src | dst x 3 6 97 x [r] r
sam8 8 ri instruction set s3c9228/p9228 6 - 28 ld ? load ld (continued) examples: given: r0 = 01h, r1 = 0ah, register 00h = 01h, register 01h = 20h, register 02h = 02h, loop = 30h, and register 3ah = 0ffh: ld r0,#10h ? r0 = 10h ld r0,01h ? r0 = 20h, register 01h = 20h ld 01h,r0 ? register 01h = 01h, r0 = 01h ld r1,@r0 ? r1 = 20h, r0 = 01h ld @r0,r1 ? r0 = 01h, r1 = 0ah, register 01h = 0ah ld 00h,01h ? register 00h = 20h, register 01h = 20h ld 02h,@00h ? register 02h = 20h, register 00h = 01h ld 00h,#0ah ? register 00h = 0ah ld @00h,#10h ? register 00h = 01h, register 01h = 10h ld @00h,02h ? register 00h = 01h, register 01h = 02, register 02h = 02h ld r0,#loop[r1] ? r0 = 0ffh, r1 = 0ah ld #loop[r0],r1 ? register 31h = 0ah, r0 = 01h, r1 = 0ah
s3c9228/p9228 s am8 8rc ri instruction set 6 - 29 ldc/lde ? load memory ldc/lde dst,src operation: dst src this instruction loads a byte from program or data memory into a working register or vice-versa. the source values are unaffected. ldc refers to program memory and lde to data memory. the assembler makes ' irr' or ' rr' values an even number for program memory and an odd number for data memory. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src 1. opc dst | src 2 10 c3 r irr 2. opc src | dst 2 10 d3 irr r 3. opc dst | src xs 3 12 e7 r xs [ rr] 4. opc src | dst xs 3 12 f7 xs [ rr] r 5. opc dst | src xl l xl h 4 14 a7 r xl [ rr] 6. opc src | dst xl l xl h 4 14 b7 xl [ rr] r 7. opc dst | 0000 da l da h 4 14 a7 r da 8. opc src | 0000 da l da h 4 14 b7 da r 9. opc dst | 0001 da l da h 4 14 a7 r da 10. opc src | 0001 da l da h 4 14 b7 da r notes: 1. the source ( src) or working register pair [ rr] for formats 5 and 6 cannot use register pair 0?1. 2. for formats 3 an d 4, the destination address 'xs [ rr]' and the source address 'xs [ rr]' are each one byte. 3. for formats 5 and 6, the destination address 'xl [ rr] and the source address 'xl [ rr]' are each two bytes. 4. the da and r source values for formats 7 and 8 are used to address program memory; the second set of values, used in formats 9 and 10, are used to address data memory.
sam8 8 ri instruction set s3c9228/p9228 6 - 30 ldc/lde ? load memory ldc/lde (continued) examples: given: r0 = 11h, r1 = 34h, r2 = 01h, r3 = 04h, r4 = 00h, r5 = 60h; program memory locations 0061 = aah, 0103h = 4fh, 0104h = 1a, 0105h = 6dh, and 1104h = 88h. external data memory locations 0061h = bbh, 0103h = 5fh, 0104h = 2ah, 0105h = 7dh, and 1104h = 98h: ldc r0,@rr2 ; r0 contents of program memory location 0104h ; r0 = 1ah, r2 = 01h, r3 = 04h lde r0,@rr2 ; r0 contents of external data memory location 0104h ; r0 = 2ah, r2 = 01h, r3 = 04h ldc * @rr2,r0 ; 11h (contents of r0) is loaded into program memory ; location 0104h (rr2), ; working registers r0, r2, r3 ? no change lde @rr2,r0 ; 11h (contents of r0) is loaded into external data memory ; location 0104h (rr2), ; working registers r0, r2, r3 ? no change ldc r0,#01h[rr4] ; r0 contents of program memory location 0061h ; (01h + rr4), ; r0 = aah, r2 = 00h, r3 = 60h lde r0,#01h[rr4] ; r0 contents of external data memory location 0061h ; (01h + rr4), r0 = bbh, r4 = 00h, r5 = 60h ldc (note) #01h[rr4],r0 ; 11h (contents of r0) is loaded into program me mory ; location 0061h (01h + 0060h) lde #01h[rr4],r0 ; 11h (contents of r0) is loaded into external data memory ; location 0061h (01h + 0060h) ldc r0,#1000h[rr2] ; r0 contents of program memory location 1104h ; (1000h + 0104h), r0 = 88h, r2 = 01h, r3 = 04h lde r0,#1000h[rr2] ; r0 contents of external data memory location 1104h ; (1000h + 0104h), r0 = 98h, r2 = 01h, r3 = 04h ldc r0,1104h ; r0 contents of program memory location 1104h, ; r0 = 88h lde r0,11 04h ; r0 contents of external data memory location 1104h, ; r0 = 98h ldc (note) 1105h,r0 ; 11h (contents of r0) is loaded into program memory ; location 1105h, (1105h) 11h lde 1105h,r0 ; 11h (contents of r0) is loaded into external data memory ; location 1105h, (1105h) 11h note: these instructions are not supported by masked rom type devices.
s3c9228/p9228 s am8 8rc ri instruction set 6 - 31 ldcd/lded ? load memory and decrement ldcd/lded dst,src operation: dst src rr rr ? 1 these instructions are used for user stacks or block transfers of data from program or data memory to the register file. the address of the memory location is specified by a working register pair. the contents of the source location are loaded into the destination location. the memory address is then decremented. the contents of the source are unaffected. ldcd references program memory and lded references external data memory. the assembler makes ? irr ? an even number for program memory and an odd number for data memory. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 10 e2 r irr examples: given: r6 = 10h, r7 = 33h, r8 = 12h, program memory location 1033h = 0cdh, and external data memory location 1033h = 0ddh: ldcd r8,@rr6 ; 0cdh (contents of program memory location 1033h) is ; loaded into r8 and rr6 is decremented by one ; r8 = 0cdh, r6 = 10h, r7 = 32h (rr6 ? rr6 - 1) lded r8,@rr6 ; 0ddh (contents of data memory location 103 3h) is ; loaded into r8 and rr6 is decremented by one ; (rr6 ? rr6 - 1) r8 = 0ddh, r6 = 10h, r7 = 32h
sam8 8 ri instruction set s3c9228/p9228 6 - 32 ldci/ldei ? load memory and increment ldci/ldei dst,src operation: dst src rr rr + 1 these instructions are used for user stacks or block transfers of data from program or data memory to the register file. the address of the memory location is specified by a working register pair. the contents of the source location are loaded into the destination location. the memory address is then incremented automatically. the contents of the source are unaffected. ldci refers to program memory and ldei refers to external data memory. the assembler makes ' irr' even for program memory and odd for data memory. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 10 e3 r irr examples: given: r6 = 10h, r7 = 33h, r8 = 12h, program memory locations 1033h = 0cdh and 1034h = 0c5h; external data memory locations 1033h = 0ddh and 1034h = 0d5h: ldci r8,@rr6 ; 0cdh (contents of program memory location 1033h) is ; loaded into r8 and rr6 is incremented by one ; (rr6 rr6 + 1) r8 = 0cdh, r6 = 10h, r7 = 34h ldei r8,@rr6 ; 0ddh (contents of data m emory location 1033h) is ; loaded into r8 and rr6 is incremented by one ; (rr6 rr6 + 1) r8 = 0ddh, r6 = 10h, r7 = 34h
s3c9228/p9228 s am8 8rc ri instruction set 6 - 33 nop ? no operation nop operation: no action is performed when the cpu executes this instruction. typic ally, one or more nops are executed in sequence in order to effect a timing delay of variable duration. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 4 ff example: when the instruction nop is encountered in a program, no operation occurs. instead, there is a delay in instruction execution time.
sam8 8 ri instruction set s3c9228/p9228 6 - 34 or ? logical or or dst,src operation: dst dst or src the source operand is logically ored with the destination operand and the result is stored in the destination. the contents of the source are unaffected. the or operation results in a "1" being stored whenever either of the corresponding bits in the two operands is a "1"; otherwise a "0" is stored. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always cleared to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 42 r r 6 43 r lr opc src dst 3 6 44 r r 6 45 r ir opc dst src 3 6 46 r im examples: given: r0 = 15h, r1 = 2ah, r2 = 01h, register 00h = 08h, register 01h = 37h, and register 08h = 8ah: or r0,r1 ? r0 = 3fh, r1 = 2ah or r0,@r2 ? r0 = 37h, r2 = 01h, register 01h = 37h or 00h,01h ? register 00h = 3fh, register 01h = 37h or 01h,@00h ? register 00h = 08h, register 01h = 0bfh or 00h,#02h ? register 00h = 0ah in the first example, if working register r0 contains the value 15h and reg ister r1 the value 2ah, the statement "or r0,r1" logical- ors the r0 and r1 register contents and stores the result (3fh) in destination register r0. the other examples show the use of the logical or instruction with the various addressing modes and formats.
s3c9228/p9228 s am8 8rc ri instruction set 6 - 35 pop ? pop from stack pop dst operation: dst @sp sp sp + 1 the contents of the location addressed by the stack pointer are loaded into the destination. the stack pointer is then incremented by one. flags: no flags affected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 8 50 r 8 51 ir examples: given: register 00h = 01h, register 01h = 1bh, sp (0d9h) = 0bbh, and stack register 0bbh = 55h: pop 00h ? register 00h = 55h, sp = 0bch pop @00h ? register 00h = 01h, register 01h = 55h, sp = 0bch in the first example, general register 00h contains the value 01h. the statement "pop 00h" loads the contents of location 0bbh (55h) into destination register 00h and then increments the stack pointer by one. register 00h then contains the value 55h and the sp points to location 0bch.
sam8 8 ri instruction set s3c9228/p9228 6 - 36 push ? push to stack push src operation: sp sp ? 1 @sp src a push instruction decrements the stack pointer value and loads the contents of the source ( src) into the location addressed by the decremented stack pointer. the operation then adds the new value to the top of the stack. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst opc src 2 8 70 r 8 71 ir examples: given: register 40h = 4fh, register 4fh = 0aah, sp = 0c0h: push 40h ? register 40h = 4fh, stack register 0bfh = 4fh, sp = 0bfh push @40h ? register 40h = 4fh, register 4fh = 0aah, stack register 0bfh = 0aah, sp = 0bfh in the first example, if the stack pointer contains the value 0c0h, and general register 40h the value 4fh, the statement "push 40h" decrements the stack pointer from 0c0 to 0bfh. it then loads the contents of register 40h into location 0bfh. register 0bfh then contains the value 4fh and sp points to location 0bfh.
s3c9228/p9228 s am8 8rc ri instruction set 6 - 37 rcf ? reset carry flag rcf rcf operation: c 0 the carry flag is cleared to logic zero, regardless of its previous value. flags: c: cleared to "0". no other flags are affected. format: bytes cycles opcode (hex) opc 1 4 cf example: given: c = "1" or "0": the instruction rcf clears the carry flag (c) to logic zero.
sam8 8 ri instruction set s3c9228/p9228 6 - 38 ret ? return ret operation: pc @sp sp sp + 2 the ret instruction is normally used to return to the previously executing procedure at the end of a procedure entered by a call instruction. the contents of the location addressed by the stack pointer are popped into the program counter. the next statement that is executed is the one that is addressed by the new program counter value. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 8 af example: given: sp = 0bch, (sp) = 101ah, and pc = 1234: ret ? pc = 101ah, sp = 0beh the statement "r et" pops the contents of stack pointer location 0bch (10h) into the high byte of the program counter. the stack pointer then pops the value in location 0bdh (1ah) into the pc's low byte and the instruction at location 101ah is executed. the stack pointer now points to memory location 0beh.
s3c9228/p9228 s am8 8rc ri instruction set 6 - 39 rl ? rotate left rl dst operation: c dst (7) dst (0) dst (7) dst (n + 1) dst (n), n = 0?6 the contents of the destination operand are rotated left one bit position. the initial value o f bit 7 is moved to the bit zero (lsb) position and also replaces the carry flag. c 7 0 flags: c: set if the bit rotated from the most significant bit position (bit 7) was "1". z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 90 r 4 91 ir examples: given: register 00h = 0aah, register 01h = 02h and register 02h = 17h: rl 00h ? register 00h = 55h, c = "1" rl @01h ? register 01h = 02h, register 02h = 2eh, c = "0" in the first example, if general register 00h contains the value 0aah (10101010b), the statement "rl 00h" rotates the 0aah value left one bit position, leaving the new value 55h (01010101b) and setting the carry and overflow flags.
sam8 8 ri instruction set s3c9228/p9228 6 - 40 rlc ? rotate left through carry rlc dst operation: dst (0) c c dst (7) dst (n + 1) dst (n), n = 0?6 the contents of the destination operand with the carry flag are rotated left one bit position. the initial value of bit 7 replaces the carry flag (c); the initial value of the carry flag replaces bit zero. c 7 0 flags: c: set if the bit rotated from the most significant bit position (bit 7) was "1". z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 10 r 4 11 ir examples: given: register 00h = 0aah, register 01h = 02h, and register 02h = 17h, c = "0": rlc 00h ? register 00h = 54h, c = "1" rlc @01h ? register 01h = 02h, register 02h = 2eh, c = "0" in the first example, if general register 00h has the value 0aah (10101010b), the statement "rlc 00h" rotates 0aah one bit position to the left. the initial value of bit 7 sets the carry flag and the initial value of the c flag replaces bit zero of register 00h, leaving the value 55h (01010101b). the msb of register 00h resets the carry flag to "1" and sets the overflow flag.
s3c9228/p9228 s am8 8rc ri instruction set 6 - 41 rr ? rotate right rr dst operation: c dst (0) dst (7) dst (0) dst (n) dst (n + 1), n = 0?6 the content s of the destination operand are rotated right one bit position. the initial value of bit zero (lsb) is moved to bit 7 (msb) and also replaces the carry flag (c). c 7 0 flags: c: set if the bit rotated from the least significant bit position (bit zero) was "1". z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 e0 r 4 e1 ir examples: given: register 00h = 31h, register 01h = 02h, and register 02h = 17h: rr 00h ? register 00h = 98h, c = "1" rr @01h ? register 01h = 02h, register 02h = 8bh, c = "1" in the first example, if general register 00h contains the value 31h (00110001b), the statement "rr 00h" rotates this value one bit position to the right. the initial value of bit zero is moved to bit 7, leaving the new value 98h (10011000b) in the destination register. the initial bit zero also resets the c flag to "1" and the sign flag and overflow flag are also set to "1".
sam8 8 ri instruction set s3c9228/p9228 6 - 42 rrc ? rotate right through carry rrc dst operation: dst (7) c c dst (0) dst (n) dst (n + 1), n = 0?6 the contents of the destination operand and the carry flag are rotated right one bit position. the initial value of bit zero (lsb) replaces the carry flag; the initial value of the carry flag replaces bit 7 (msb). c 7 0 flags: c: set if the bit rotated from the least significant bit position (bit zero) was "1". z: set if the result is "0" cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 c0 r 4 c1 ir examples: given: register 00h = 55h, register 01h = 02h, register 02h = 17h, and c = "0": rrc 00h ? register 00h = 2ah, c = "1" rrc @01h ? register 01h = 02h, register 02h = 0bh, c = "1" in the first example, if general register 00h contains the value 55h (01010101b), the statement "rrc 00h" rotates this value one bit position to the right. the initial value of bit zero ("1") replaces the carry flag and the initial value of the c f lag ("1") replaces bit 7. this leaves the new value 2ah (00101010b) in destination register 00h. the sign flag and overflow flag are both cleared to "0".
s3c9228/p9228 s am8 8rc ri instruction set 6 - 43 sbc ? subtract with carry sbc dst,src operation: dst dst ? src ? c the source operand, along with the current value of the carry flag, is subtracted from the destination operand and the result is stored in the destination. the contents of the source are unaffected. subtraction is performed by adding the two's-complement of the source operand to the destination operand. in multiple precision arithmetic, this instruction permits the carry ("borrow") from the subtraction of the low-order operands to be subtracted from the subtraction of high-order operands. flags: c: set if a borrow occurred ( src > dst); cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the operands were of opposite sign and the sign f the result is the same as the sign of the source; cleared otherwise. d: always set to "1". h: cleared if there is a carry from the most significant bit of the low-order four bits of the result; set otherwise, indicating a "borrow". format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 32 r r 6 33 r lr opc src dst 3 6 34 r r 6 35 r ir opc dst src 3 6 36 r im examples: given: r1 = 10h, r2 = 03h, c = "1", register 01h = 20h, register 02h = 03h, and reg ister 03h = 0ah: sbc r1,r2 ? r1 = 0ch, r2 = 03h sbc r1,@r2 ? r1 = 05h, r2 = 03h, register 03h = 0ah sbc 01h,02h ? register 01h = 1ch, register 02h = 03h sbc 01h,@02h ? register 01h = 15h,register 02h = 03h, register 03h = 0ah sbc 01h,#8ah ? register 01h = 95h; c, s, and v = "1" in the first example, if working register r1 contains the value 10h and register r2 the value 03h, the statement "sbc r1,r2" subtracts the source value (03h) and the c flag value ("1") from the destination (10h) and then stores the result (0ch) in register r1.
sam8 8 ri instruction set s3c9228/p9228 6 - 44 scf ? set carry flag scf operation: c 1 the carry flag (c) is set to logic one, regardless of its previous value. flags: c: set to "1". no other flags are affected. format: bytes cycles opcode (hex) opc 1 4 df example: the statement scf sets the carry flag to logic one.
s3c9228/p9228 s am8 8rc ri instruction set 6 - 45 sra ? shift right arithmetic sra dst operation: dst (7) dst (7) c dst (0) dst (n) dst (n + 1), n = 0?6 an arithmetic shift-right of one bit position is perform ed on the destination operand. bit zero (the lsb) replaces the carry flag. the value of bit 7 (the sign bit) is unchanged and is shifted into bit position 6. c 7 6 0 flags: c: set if the bit shifted from the lsb position (bit zero) was "1". z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: always cleared to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 d0 r 4 d1 ir examples: given: register 00h = 9ah, register 02h = 03h, register 03h = 0bch, and c = "1": sra 00h ? register 00h = 0cd, c = "0" sra @02h ? register 02h = 03h, register 03h = 0deh, c = "0" in the first example, if general register 00h contains the value 9ah (10011010b), the statement "sra 00h" shifts the bit values in register 00h right one bit position. bit zero ("0") clears the c flag and bit 7 ("1") is then shifted into the bit 6 position (bit 7 remains unchanged). this leaves the value 0cdh (11001101b) in destination register 00h.
sam8 8 ri instruction set s3c9228/p9228 6 - 46 stop ? stop operation stop operation: the stop instruction stops both the cpu clock and system clock and causes the microcontroller to enter stop mode. during stop mode, the contents of on-chip cpu registers, peripheral registers, and i/o port control and data registers are retained. stop mode can be released by an external reset operation or external interrupt input. for the reset operation, the reset pin must be held to low level until the required oscillation stabilization interval has elapsed. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc 1 4 7f ? ? example: the statement stop halts all microcontroller operations.
s3c9228/p9228 s am8 8rc ri instruction set 6 - 47 sub ? subtract sub dst,src operation: dst dst ? src the source operand is subtracted from the destination operand and the result is stored in the destination. the contents of the source are unaffected. subtraction is performed by adding the two's complement of the source operand to the destination operand. flags: c: set if a "borrow" occurred; cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the operands were of opposite signs and the sign of the result is of the same as the sign of the source operand; cleared otherwise. d: always set to "1". h: cleared if there is a carry from the most significant bit of the low-order four bits of the result; set otherwise indicating a "borrow". format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 22 r r 6 23 r lr opc src dst 3 6 24 r r 6 25 r ir opc dst src 3 6 26 r im examples: given: r1 = 12h, r2 = 03h, register 01h = 21h, register 02h = 03h, register 03h = 0ah: sub r1,r2 ? r1 = 0fh, r2 = 03h sub r1,@r2 ? r1 = 08h, r2 = 03h sub 01h,02h ? register 01h = 1eh, register 02h = 03h sub 01h,@02h ? register 01h = 17h, register 02h = 03h sub 01h,#90h ? register 01h = 91h; c, s, and v = "1" sub 01h,#65h ? register 01h = 0bch; c and s = "1", v = "0" in the first example, if working register r1 contains the value 12h and if register r2 contains the value 03h, the statement "sub r1,r2" subtracts the source value (03h) from the destination value (12h) and stores the result (0fh) in destination register r1.
sam8 8 ri instruction set s3c9228/p9228 6 - 48 tcm ? test complement under mask tcm dst,src operation: (not dst) and src thi s instruction tests selected bits in the destination operand for a logic one value. the bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask). the tcm statement complements the destination operand, which is then anded with the source mask. the zero (z) flag can then be checked to determine the result. the destination and source operands are unaffected. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always cleared to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 62 r r 6 63 r lr opc src dst 3 6 64 r r 6 65 r ir opc dst src 3 6 66 r im examples: given: r0 = 0c7h, r1 = 02h, r2 = 12h, register 00h = 2bh, register 01h = 02h, and register 02h = 23h: tcm r0,r1 ? r0 = 0c7h, r1 = 02h, z = "1" tcm r0,@r1 ? r0 = 0c7h, r1 = 02h, re gister 02h = 23h, z = "0" tcm 00h,01h ? register 00h = 2bh, register 01h = 02h, z = "1" tcm 00h,@01h ? register 00h = 2bh, register 01h = 02h, register 02h = 23h, z = "1" tcm 00h,#34 ? register 00h = 2bh, z = "0" in the first example, if working register r0 contains the value 0c7h (11000111b) and register r1 the value 02h (00000010b), the statement "tcm r0,r1" tests bit one in the destination register for a "1" value. because the mask value corresponds to the test bit, the z flag is set to logic one and can be tested to determine the result of the tcm operation.
s3c9228/p9228 s am8 8rc ri instruction set 6 - 49 tm ? test under mask tm dst,src operation: dst and src this instruction tests selected bits in the destination operand for a logic zero value. the bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask), which is anded with the destination operand. the zero (z) flag can then be checked to determine the result. the destination and source operands are unaffected. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always reset to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 72 r r 6 73 r lr opc src dst 3 6 74 r r 6 75 r ir opc dst src 3 6 76 r im examples: given: r0 = 0c7h, r1 = 02h, r2 = 18h, register 00h = 2bh, register 01h = 02h, and register 02h = 23h: tm r0,r1 ? r0 = 0c7h, r1 = 02h, z = "0" tm r0,@r1 ? r0 = 0c7h, r1 = 02h, register 02h = 23h, z = "0" tm 00h,01h ? register 00h = 2bh, register 01h = 02h, z = "0" tm 00h,@01h ? register 00h = 2bh, register 01h = 02h, register 02h = 23h, z = "0" tm 00h,#54h ? register 00h = 2bh, z = "1" in the first example, if working register r0 contains the value 0c7h (11000111b) and register r1 the value 02h (00000010b), the statement "tm r0,r1" tests bit one in the destination register for a "0" value. because the mask value does not match the test bit, the z flag is cleared to logic zero and can be tested to determine the result of the tm operation.
sam8 8 ri instruction set s3c9228/p9228 6 - 50 xor ? logical exclusive or xor dst,src operation: dst dst xor src the source operand is logically exclusive- ored with the destination operand and the result is stored in the destination. the exclusive-or operation results in a "1" bit being stored whenever the corresponding bits in the operands are different; otherwise, a "0" bit is stored. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always reset to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 b2 r r 6 b3 r lr opc src dst 3 6 b4 r r 6 b5 r ir opc dst src 3 6 b6 r im examples: given: r0 = 0c7h, r1 = 02h, r2 = 18h, register 00h = 2bh, register 01h = 02h, and register 02h = 23h: xor r0,r1 ? r0 = 0c5h, r1 = 02h xor r0,@r1 ? r0 = 0e4h, r1 = 02h, register 02h = 23h xor 00h,01h ? register 00h = 29h, register 01h = 02h xor 00h,@01h ? register 00h = 08h, register 01h = 02h, register 02h = 23h xor 00h,#54h ? register 00h = 7fh in the first example, if working register r0 contains the value 0c7h and if register r1 contains the value 02h, the statement "xor r0,r1" logically exclusive- ors the r1 value with the r0 value and stores the result (0c5h) in the destination register r0.
s3c9228/p9228 clock circuits 7- 1 7 clock circuits overview the s3c9228 microcontroller has two oscillator circuits: a main clock, and a sub clock circuit. the cpu and peripheral hardware operate on the system clock frequency supplied through these circuits. the maximum cpu clock frequency, is determined by clkcon register settings . system clock circuit the system clock circuit has the following components: ? c rystal , ceramic resonator , rc oscillation source (main clock only), or an external clock ? oscillator stop and wake-up functions ? programmable frequency divider for the cpu clock ( f xx divided by 1, 2, 8, or 16 ) ? clock circuit control register, clkcon ? oscillator control register, osccon cpu clock notation in this document, the following notation is used for descriptions of the cpu clock: fx main clock fxt sub clock fxx selected system clock
clock circuits s3c9 228/p9228 7- 2 main oscillator circuits x in x out figure 7-1. crystal/ceramic oscillator x in x out figure 7-2. external oscillator x in x out r figure 7-3. rc oscillator sub oscillator circuits xt in xt out 32.768 khz figure 7-4. crystal/ceramic oscillator xt in xt out figure 7-5. external oscillator
s3c9228/p9228 clock circuits 7- 3 clock status during power-down modes the two power-down modes, stop mode and idle mode, affect the system clock as follows: ? in stop mode, the main oscillator is halted. stop mode is released, and the oscillator started, by a reset operation, by an external interrupt, or by an internal interrupt if sub clock is selected as the clock source (when the fx is selected as system clock). ? in idle mode, the internal clock signal is gated away from the cpu, but continues to be supplied to the interrupt structure, timer a/b, and watch timer. idle mode is released by a reset or by an external or internal interrupts. 1/8-1/4096 frequency dividing circuit stop release main-system oscillator circuit selector 1 f x f x t stop sub-system oscillator circuit int osccon.0 osccon.3 osccon.2 1/1 1/16 1/2 1/8 selector 2 stpcon stop osc inst. f xx clkcon.4-.3 cpu stop watch timer basic timer timer/counters watch timer lcd controller a/d converter sio lcd controller figure 7-6. system clock circuit diagram
clock circuits s3c9 228/p9228 7- 4 system clock control register (clkcon) the system clock control register, clkcon, is located in address d4h. it is read/write addressable and has the following functions: ? oscillator irq wake-up function enable/disable ? oscillator frequency divide-by value clkcon register settings control whether or not an external interrupt can be used to trigger a stop mode release (this is called the ?irq wake-up? function). the irq ?wake-up? enable bit is clkcon.7. after a reset, the external interrupt oscillator wake-up function is enabled, the main oscillator is activated, and the f x /16 (the slowest clock speed) is selected as the cpu clock. if necessary, you can then increase the cpu clock speed to f x , f x /2, or f x /8 by setting the clkcon, and you can change system clock from main clock to sub clock by setting the osccon. system clock control register (clkcon) d4h, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb not used for s3c9228 (must keep always "0") divide-by selection bits for cpu clock frequency: 00 = f xx/16 01 = f xx/8 10 = f x x/2 11 = f xx oscillator irq wake-up enable bit: 0 = enable irq for main oscillator wake-up function in power down mode 1 = disable irq for main oscillator wake-up function in power down mode not used for s3c92228 (must keep always "0") figure 7-7. system clock control register (clkcon)
s3c9228/p9228 clock circuits 7- 5 oscillator control register (osccon) the oscillator control register, osccon, is located in address d3h. it is read/write addressable and has the following functions: ? system clock selection ? main oscillator control ? sub oscillator control osccon.0 register settings select main clock or sub clock as system clock. after a reset, main clock is selected for system clock because the reset value of osccon.0 is "0". the main oscillator can be stopped or run by setting osccon.3. the sub oscillator can be stopped or run by setting osccon.2. oscillator control register (osccon) d3h, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb not used for s3c9228 main oscillator control bit: 0 = main oscillator run 1 = main oscillator stop sub oscillator control bit: 0 = sub oscillator run 1 = sub oscillator stop not used for s3c9228 system clock selection bit: 0 = main oscillator select 1 = sub oscillator select figure 7-8. oscillator control register (osccon)
clock circuits s3c9 228/p9228 7- 6 switching the cpu clock data loadings in the oscillator control register, osccon, determine whether a main or a sub clock is selected as the cpu clock, and also how this frequency is to be divided by setting clkcon. this makes it possible to switch dynamically between main and sub clocks and to modify operating frequencies. osccon.0 select the main clock ( fx) or the sub clock ( fxt) for the system clock. osccon .3 start or stop main clock oscillation, and osccon.2 start or stop sub clock oscillation. clkcon.4?.3 control the frequency divider circuit, and divide the selected fxx clock by 1, 2, 8, or 16. for example, you are using the default system clock (normal operating mode and a main clock of fx/16) and you want to switch from the fx clock to a sub clock and to stop the main clock. to do this, you need to set osccon.0 to "1", take a delay, and osccon.3 to "1" sequently. this switches the clock from fx to fxt and stops main clock oscillation. the following steps must be taken to switch from a sub clock to the main clock: first, set osccon.3 to "0" to enable main system clock oscillation. then, after a certain number of machine cycles has elapsed, select the main clock by setting osccon.0 to "0". + + programming tip ? switching the cpu clock 1. this example shows how to change from the main clock to the sub clock: ma2sub or osccon,#01h ; switches to the sub clock call dly16 ; delay 16ms or osccon,#08h ; stop the main clock osc illation ret 2. this example shows how to change from sub clock to main clock: sub2ma and osccon,#0f7h ; start the main clock oscillation call dly16 ; delay 16 ms and osccon,#0feh ; switch to the main clock ret dly16 ld r0,#20h del nop dec r0 jr nz,del ret
s3c9228/p9228 clock circuits 7- 7 stop control register (stpcon) the stop control register, stpcon, is located in address e0h. it is read/write addressable and has the following functions: ? enable/disable stop instruction after a reset, the stop instruction is disabled, because the value of stpcon is "other values". if necessary, you can use the stop instruction by setting the value of stpcon to "10100101b". stop control register (stpcon) e0h, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb stop control bits: 10100101 = enable stop instruction other values = disable stop instruction figure 7-9. stop control register (stpcon) + + programming tip ? how to use stop instruction this example shows how to go stop mode when a main clock is selected as the system clock. ld stopcon,#1010010b ; enable stop instruction stop ; enter stop mode nop nop nop ; release stop mode ld stopcon,#00000000b ; disable stop instruction
clock circuits s3c9 228/p9228 7- 8 notes
s3c9228/p9228 reset reset and power-down 8- 1 8 reset reset and power-down system reset overview during a power-on reset, the voltage at v dd goes to high level and the reset pin is forced to low level. the reset signal is input through a schmitt trigger circuit where it is then synchronized with the cpu clock. this procedure brings s3c9228/p9228 into a known operating status. to allow time for internal cpu clock oscillation to stabilize, the reset pin must be held to low level for a minimum time interval after the power supply comes within tolerance. the minimum required oscillation stabilization time for a reset operation is 1 millisecond. whenever a reset occurs during normal operation (that is, when both v dd and reset are high level), the reset pin is forced low and the reset operation starts. all system and peripheral control registers are then reset to their default hardware values (see table 8-1). in summary, the following sequence of events occurs during a reset operation: ? all interrupts are disabled. ? the watchdog function (basic timer) is enabled. ? the p0.0?p0.3, p1, and p2.2?p2.3 are set to schmitt trigger input mode and all pull-up resistors are disabled for the i/o port pin circuits. ? peripheral control and data re gisters are disabled and reset to their default hardware values. ? the program counter (pc) is loaded with the program reset address in the rom, 0100h. ? when the programmed oscillation stabilization time interval has elapsed, the instruction stored in rom location 0100h (and 0101h) is fetched and executed. note to program the duration of the oscillation stabilization interval, you make the appropriate settings to the basic timer control register, btcon, before entering stop mode. also, if you do not want to use the basic timer watchdog function (which causes a system reset if a basic timer counter overflow occurs), you can disable it by writing '1010b' to the upper nibble of btcon.
reset reset and power-down s3c9228 /p9228 8- 2 power-down modes stop mode stop mode is invoked by the instruction stop. in stop mode, the operation of the cpu and main oscillator is halted. all peripherals which the main oscillator is selected as a clock source stop also because main oscillator stops. but the watch timer and lcd controller will not halted in stop mode if the sub clock is selected as watch timer clock source. the data stored in the internal register file are retained in stop mode. stop mode can be released in one of three ways: by a system reset, by an internal watch timer interrupt (when sub clock is selected as clock source of watch timer), or by an external interrupt. example: ld stopcon,#10100101b stop nop nop nop ld stopcon,#00000000b notes 1. do not use stop mode if you are using an external clock source because x in input must be restricted internally to v ss to reduce current leakage. 2. in application programs, a stop instruction must be immediately followed by at least three nop instructions. this ensures an adequate time interval for the clock to stabilize before the next instruction is executed. if three or more nop instructions are not used after stop instruction, leakage current could be flown because of the floating state in the internal bus. 3. to enable/disable stop instruction, the stopcon register should be written with 10100101b/other values before/after stop instruction. using reset to release stop mode stop mode is released when the reset signal goes active (low level): all system and peripheral control registers are reset to their default hardware values and the contents of all data registers are retained. when the programmed oscillation stabilization interval has elapsed, the cpu starts the system initialization routine by fetching the program instruction stored in rom location 0100h. using an external interrupt to release stop mode external interrupts can be used to release stop mode. for the s3c9228 microcontroller, we recommend using the int interrupt, p0, p1, and p3.
s3c9228/p9228 reset reset and power-down 8- 3 using an internal interrupt to release stop mode an internal interrupt, watch timer, can be used to release stop mode because the watch timer operates in stop mode if the clock source of watch timer is sub clock. if system clock is sub clock, you can't use any interrupts to release stop mode. that is, you had better use the idle instruction instead of stop one when sub clock is selected as the system clock. please note the following conditions for stop mode release: ? if you release stop mode using an internal or external interrupt, the current values in system and peripheral control registers are unchanged. ? if you use an internal or external interrupt for stop mode release, you can also program the duration of the oscillation stabilization interval. to do this, you must make the appropriate control and clock settings before entering stop mode. ? if you use an interrupt to release stop mode, the bit-pair setting for clkcon.4/clkcon.3 remains unchanged and the currently selected clock value is used. ? the internal or external interrupt is serviced when the stop mode release occurs. following the iret from the service routine, the instruction immediately following the one that initiated stop mode is executed. idle mode idle mode is invoked by the instruction idle ( opcode 6fh). in idle mode, cpu operations are halted while some peripherals remain active. during idle mode, the internal clock signal is gated away from the cpu and from all but the following peripherals, which remain active: ? interrupt logic ? basic timer ? timer 1 (timer a and b) ? watch timer ? lcd controller i/o port pins retain the mode (input or output) they had at the time idle mode was entered. idle mode release you can release idle mode in one of two ways: 1. execute a reset. all system and peripheral c ontrol registers are reset to their default values and the contents of all data registers are retained. the reset automatically selects the slowest clock (1/16) because of the hardware reset value for the clkcon register. if all external interrupts are masked in the imr register, a reset is the only way you can release idle mode. 2. activate any enabled interrupt ? internal or external. when you use an interrupt to release idle mode, the 2 -bit clkcon.4/clkcon.3 value remains unchanged, and the currently selected clock value is used. the interrupt is then serviced. when the return-from-interrupt condition (iret) occurs, the instruction immediately following the one which initiated idle mode is executed.
reset reset and power-down s3c9228 /p9228 8- 4 hardware reset reset values table 8-1 list the values for cpu and system registers, peripheral control registers, and peripheral data registers following a reset operation in normal operating mode. the following notation is used in these table to represent specific reset values: ? a "1" or a "0" shows the reset bit value as logic one or logic zero, respectively. ? an 'x' means that the bit value is undefined following reset . ? a dash ('?') means that the bit is either not used or not mapped. table 8-1. register values after reset reset register name mnemonic address bit values after reset reset dec hex 7 6 5 4 3 2 1 0 locations b8h?b9h are not mapped. timer b control register tbcon 202 bah ? 0 0 0 0 0 0 ? timer 1/a control register tacon 203 bbh 0 0 0 0 0 0 0 ? timer b data register tbdata 204 bch 1 1 1 1 1 1 1 1 timer a data register tadata 205 bdh 1 1 1 1 1 1 1 1 timer b counter tbcnt 206 beh 0 0 0 0 0 0 0 0 timer a counter tacnt 207 bfh 0 0 0 0 0 0 0 0 a/d converter control register adcon 208 d0h ? ? 0 0 0 0 0 0 a/d converter data register (high byte) addatah 209 d1h x x x x x x x x a/d converter data register (low byte) addatal 210 d2h ? ? ? ? ? ? x x oscillator control register osccon 211 d3h ? ? ? ? 0 0 ? 0 system clock control register clkcon 212 d4h 0 0 0 0 0 0 0 0 system flags register flags 213 d5h x x x x ? ? ? ? interrupt pending register 1 intpnd1 214 d6h 0 0 0 0 0 0 0 0 interrupt pending register 2 intpnd2 215 d7h ? ? 0 0 0 0 0 0 lcd port control register lopt 216 d8h ? 0 0 0 0 0 0 0 stack pointer sp 217 d9h x x x x x x x x watch timer control register wtcon 218 dah 0 0 0 0 0 0 0 ? locations dbh is not mapped. basic timer control register btcon 220 dch 0 0 0 0 0 0 0 0 basic timer counter btcnt 221 ddh 0 0 0 0 0 0 0 0 locations deh is not mapped.
s3c9228/p9228 reset reset and power-down 8- 5 table 8-1. register values after reset reset (continued) register name mnemonic address bit values after reset reset dec hex 7 6 5 4 3 2 1 0 system mode register sym 223 dfh ? ? ? ? 0 0 0 0 stop control register stpcon 224 e0h 0 0 0 0 0 0 0 0 sio control register siocon 225 e1h 0 0 0 0 0 0 0 ? sio data register siodata 226 e2h 0 0 0 0 0 0 0 0 sio prescaler register siops 227 e3h 0 0 0 0 0 0 0 0 port 0 data register p0 228 e4h 0 0 0 0 0 0 0 0 port 1 data register p1 229 e5h 0 0 0 0 0 0 0 0 port 2 data register p2 230 e6h 0 0 0 0 0 0 0 0 port 3 data register p3 231 e7h 0 0 0 0 0 0 0 0 port 4 data register p4 232 e8h 0 0 0 0 0 0 0 0 port 5 data register p5 233 e9h 0 0 0 0 0 0 0 0 port 6 data register p6 234 eah 0 0 0 0 0 0 0 0 port 0 control register p0con 235 ebh 0 0 0 0 0 0 0 0 port 0 pull-up resistors enable register p0pur 236 ech ? ? ? ? 0 0 0 0 port 0 interrupt control register p0int 237 edh ? ? ? ? 0 0 0 0 port 0 interrupt edge selection register p0edge 238 eeh ? ? ? ? 0 0 0 0 port 1 control register p1con 239 efh 0 0 0 0 0 0 0 0 port 1 pull-up resistors enable register p1pur 240 f0h ? ? ? ? 0 0 0 0 port 1 interrupt control register p1int 241 f1h ? ? ? ? 0 0 0 0 port 1 interrupt edge selection register p1edge 242 f2h ? ? ? ? 0 0 0 0 port 2 control register p2con 243 f3h 0 0 0 0 0 0 0 0 port 2 pull-up resistors enable register p2pur 244 f4h ? ? ? ? 0 0 0 0 port 3 control register p3con 245 f5h ? ? ? ? 0 0 0 0 port 3 pull-up resistors enable register p3pur 246 f6h ? ? ? ? ? ? 0 0 port 3 interrupt control register p3int 247 f7h ? ? ? ? ? ? 0 0 port 3 interrupt edge selection register p3edge 248 f8h ? ? ? ? ? ? 0 0 port 4 control register (high byte) p4conh 249 f9h 0 0 0 0 0 0 0 0 port 4 control register (high byte) p4conl 250 fah 0 0 0 0 0 0 0 0 port 5 control register (high byte) p5conh 251 fbh 0 0 0 0 0 0 0 0 port 5 control register (high byte) p5conl 252 fch 0 0 0 0 0 0 0 0 port 6 control register p6con 253 fdh 0 0 0 0 0 0 0 0 lcd mode register lmod 254 feh ? 0 0 0 0 0 0 0 location ffh is not mapped.
reset reset and power-down s3c9228 /p9228 8- 6 notes
s3c9228/p9228 i/o p orts 9- 1 9 i/o ports overview the s3c9228/p9228 microcontroller has seven bit-programmable i/o ports, p0-p6. port 0 is 6-bit port, port 1, port 2, and port 6 are 4-bit ports, port 3 is 2-bit port, and port 4 and port 5 are 8-bit ports. this gives a total of 36 i/o pins. each port can be flexibly configured to meet application design requirements. the cpu accesses ports by directly writing or reading port registers. no special i/o instructions are required. all ports of the s3c9228/p9228 except p0.4 and p0.5 can be configured to input or output mode. all lcd signal pins are shared with normal i/o ports. table 9-1 gives you a general overview of s3c9228 i/o port functions. table 9-1. s3c9228 port configuration overview port configuration options 0 1-bit programmable i/o port except p0.4 and p0.5. schmitt trigger input or push-pull, open-drain output and software assignable pull-ups. the p0.4 and p0.5 are only push-pull output ports. alternatively p0.0-p0.3 can be used as input for external interrupts int and can be used as taout, t1clk, and buz. 1 1-bit programmable i/o port. schmitt trigger input or push-pull, open-drain output and software assignable pull-ups. alternatively p1 can be used as input for external interrupts int and can be used as ad0-ad3. 2 1-bit programmable i/o port. schmitt trigger input or push-pull, open-drain output and software assignable pull-ups. alternatively p2.0 and p2.1 can be used as outputs for lcd segment signals and p2.0-p2.2 can be used as sck, so, and si. 3 1-bit programmable i/o port. schmitt trigger input or push-pull, open-drain output and software assignable pull-ups. alternatively p3 can be used as input for external interrupts intp and can be used as outputs for lcd segment signals. 4 1-bit programmable i/o port. input or push-pull, open-drain output and software assignable pull-ups. alternatively p4 can be used as outputs for lcd segment signals. 5 1-bit programmable i/o port. input or push-pull, open-drain output and software assignable pull-ups. alternatively p5.0-p5.3 can be used as outputs for lcd segment signals and p5.4-p5.7 can be used as outputs for lcd common or segment signals. 6 1-bit programmable i/o port. input or push-pull, open-drain output and software assignable pull-ups. alternatively p6 can be used as outputs for lcd common signals.
i/o ports s3c9228/p 9228 9- 2 port data registers table 9-2 gives you an overview of the register locations of all seven s3c9228 i/o port data registers. data registers for ports 1, 2, 3, 4, 5, and 6 have the general format shown in figure 9-1. table 9-2. port data register summary register name mnemonic decimal hex r/w port 0 data register p0 228 e4h r/w port 1 data register p1 229 e5h r/w port 2 data register p2 230 e6h r/w port 3 data register p3 231 e7h r/w port 4 data register p4 232 e8h r/w port 5 data register p5 233 e9h r/w port 6 data register p6 234 eah r/w msb s3c9228 i/o port data register format (n = 0-6) .7 .6 .5 .4 .3 .2 .1 .0 lsb pn.7 pn.6 pn.5 pn.4 pn.3 pn.2 pn.1 pn.0 figure 9-1. s3c9228 i/o port data register format
s3c9228/p9228 i/o p orts 9- 3 port 0 port 0 is an 6-bit i/o port with individually configurable pins. port 0 pins are accessed directly by writing or reading the port 0 data register, p0 at location e4h in page 0. p0.0-p0.3 can serve as inputs (with or without pull- up), as outputs (push-pull or open-drain) or you can be configured the following functions. ? low-nibble pins (p0.0-p0.3): taout,t1clk, buz, int ? high-nibble pins (p0.4-p0.5): push-pull output ports (only 44-qfp package) port 0 control register (p0con) port 0 has a 8-bit control register: p0con for p0.0-p0.3. a reset clears the p0con register to ?00h?, configuring pins to input mode. you use control register setting to select input or output mode (push-pull or open-drain) and enable the alternative functions. when programming this port, please remember that any alternative peripheral i/o function you configure using the port 0 control register must also be enabled in the associated peripheral module. port 0 pull-up resistor control register (p0pur) using the port 0 pull-up resistor control register, p0pur (ech, page 0), you can configure pull-up resistors to individual port 0 pins. port 0 interrupt enable, pending, and edge selection registers (p0int, intpnd1.3-.0, p0edge) to process external interrupts at the port 0 pins, three additional control registers are provided: the port 0 interrupt enable register p0int (edh, page 0), the port 0 interrupt pending bits intpnd1.3-.0 (d6h, page 0), and the port 0 interrupt edge selection register p0edge (eeh, page 0). the port 0 interrupt pending register bits lets you check for interrupt pending conditions and clear the pending condition when the interrupt service routine has been initiated. the application program detects interrupt requests by polling the intpnd1.3-.0 register at regular intervals. when the interrupt enable bit of any port 0 pin is "1", a rising or falling edge at that pin will generate an interrupt request. the corresponding intpnd1 bit is then automatically set to "1" and the irq level goes low to signal the cpu that an interrupt request is waiting. when the cpu acknowledges the interrupt request, application software must the clear the pending condition by writing a "0" to the corresponding intpnd1 bit.
i/o ports s3c9228/p 9228 9- 4 port 0 control register (p0con) ebh, page 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p0.3/buz (int) p0con bit-pair pin configuration settings: 00 01 10 11 n-channel open-drain output mode alternative function (taout, buz) p0.2 (int) p0.1/t1clk (int) p0.0/taout (int) push-pull output mode schmitt trigger input mode (t1clk) figure 9-2. port 0 control register (p0con) port 0 interrupt control register (p0int) edh, page 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb not used p0int bit configuration settings: 0 1 p0.3 (int) enable interrupt disable interrupt p0.2 (int) p0.1 (int) p0.0 (int) figure 9-3. port 0 interrupt control register (p0int)
s3c9228/p9228 i/o p orts 9- 5 port 0 interrupt pending bits (intpnd1.3-.0) d6h, page 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb intpnd1 bit configuration settings: 0 1 p0.3 (int) interrupt is pending (when read) no interrupt pending (when read), clear pending bit (when write) p0.2 (int) p0.1 (int) p0.0 (int) p1.3 (int) p1.2 (int) p1.1 (int) p1.0 (int) figure 9-4. port 0 interrupt pending bits (intpnd1.3-.0) port 0 interrupt edge selection register (p0edge) eeh, page 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p0edge bit configuration settings: 0 1 p0.3 (int) rising edge detection falling edge detection p0.2 (int) p0.1 (int) p0.0 (int) not used figure 9-5. port 0 interrupt edge selection register (p0edge) port 0 pull-up control register (p0pur) ech, page 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p0pur bit configuration settings: 0 1 enable pull-up resistor disable pull-up resistor not used p0.3 p0.2 p0.1 p0.0 figure 9-6. port 0 pull-up control register (p0pur)
i/o ports s3c9228/p 9228 9- 6 port 1 port 1 is an 4-bit i/o port with individually configurable pins. port 1 pins are accessed directly by writing or reading the port 1 data register, p1 at location e5h in page 0. p1.0-p1.3 can serve as inputs (with or without pull- up), as outputs (push-pull or open-drain) or you can be configured the following functions. ? low-nibble pins (p1.0-p1.3): ad0-ad3, int port 1 control register (p1con) port 1 has a 8-bit control register: p1con for p1.0-p1.3. a reset clears the p1con register to "00h", configuring pins to input mode. you use control register setting to select input or output mode (push-pull or open-drain) and enable the alternative functions. when programming this port, please remember that any alternative peripheral i/o function you configure using the port 1 control register must also be enabled in the associated peripheral module. port 1 pull-up resistor control register (p1pur) using the port 1 pull-up resistor control register, p1pur (f0h, page 0), you can configure pull-up resistors to individual port 1 pins. port 1 interrupt enable, pending, and edge selection registers (p1int, intpnd1.7-.4, p1edge) to process external interrupts at the port 1 pins, three additional control registers are provided: the port 1 interrupt enable register p1int (f1h, page 0), the port 1 interrupt pending bits intpnd1.7-.4 (d6h, page 0), and the port 1 interrupt edge selection register p1edge (f2h, page 0). the port 1 interrupt pending register bits lets you check for interrupt pending conditions and clear the pending condition when the interrupt service routine has been initiated. the application program detects interrupt requests by polling the intpnd1.7-.4 register at regular intervals. when the interrupt enable bit of any port 1 pin is "1", a rising or falling edge at that pin will generate an interrupt request. the corresponding intpnd1 bit is then automatically set to "1" and the irq level goes low to signal the cpu that an interrupt request is waiting. when the cpu acknowledges the interrupt request, application software must the clear the pending condition by writing a "0" to the corresponding intpnd1 bit. port 1 control register (p1con) efh, page 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p1.3/ad3 (int) p1con bit-pair pin configuration settings: 00 01 10 11 n-channel open-drain output mode alternative function (ad0,ad1, ad2, ad3) p1.2/ad2 (int) p1.1/ad1 (int) p1.0/ad0 (int) push-pull output mode schmitt trigger input mode figure 9-7. port 1 control register (p1con)
s3c9228/p9228 i/o p orts 9- 7 port 1 interrupt control register (p1int) f1h, page 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb not used p1int bit configuration settings: 0 1 p1.3 (int) enable interrupt disable interrupt p1.2 (int) p1.1 (int) p1.0 (int) figure 9-8. port 1 interrupt control register (p1int) port 1 interrupt pending bits (intpnd1.7-.4) d6h, page 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb intpnd1 bit configuration settings: 0 1 p0.3 (int) interrupt is pending (when read) no interrupt pending (when read), clear pending bit (when write) p0.2 (int) p0.1 (int) p0.0 (int) p1.3 (int) p1.2 (int) p1.1 (int) p1.0 (int) figure 9-9. port 1 interrupt pending bits (intpnd1.7-.4)
i/o ports s3c9228/p 9228 9- 8 port 1 interrupt edge selection register (p1edge) f2h, page 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p1edge bit configuration settings: 0 1 p1.3 (int) rising edge detection falling edge detection p1.2 (int) p1.1 (int) p1.0 (int) not used figure 9-10. port 1 interrupt edge selection register (p1edge) port 1 pull-up control register (p1pur) f0h, page 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p1pur bit configuration settings: 0 1 enable pull-up resistor disable pull-up resistor not used p1.3 p1.2 p1.1 p1.0 figure 9-11. port 1 pull-up control register (p1pur)
s3c9228/p9228 i/o p orts 9- 9 port 2 port 2 is an 4-bit i/o port with individually configurable pins. port 2 pins are accessed directly by writing or reading the port 2 data register, p2 at location e6h in page 0. p2.0-p2.3 can serve as inputs (with or without pull- up), as outputs (push-pull or open-drain) or you can be configured the following functions. ? low-nibble pins (p2.0-p2.3): sck, so, si, seg0-seg1 port 2 control register (p2con) port 2 has a 8-bit control register: p2con for p2.0-p2.3. a reset clears the p2con register to "00h", configuring pins to input mode. you use control register setting to select input or output mode (push-pull or open-drain) and enable the alternative functions. when programming this port, please remember that any alternative peripheral i/o function you configure using the port 2 control register must also be enabled in the associated peripheral module. port 2 pull-up resistor control register (p2pur) using the port 2 pull-up resistor control register, p2pur (f4h, page 0), you can configure pull-up resistors to individual port 2 pins. port 2 control register (p2con) f3h, page 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p2.3 p2con bit-pair pin configuration settings: 00 01 10 11 n-channel open-drain output mode alternative function (sck, so) p2.2/si p2.1/so/seg0 p2.0/sck/seg1 push-pull output mode schmitt trigger input mode (si,sck) figure 9-12. port 2 control register (p2con)
i/o ports s3c9228/p 9228 9- 10 port 2 pull-up control register (p2pur) f4h, page 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p2pur bit configuration settings: 0 1 enable pull-up resistor disable pull-up resistor not used p2.3 p2.2 p2.1 p2.0 figure 9-13. port 2 pull-up control register (p2pur)
s3c9228/p9228 i/o p orts 9- 11 port 3 port 3 is an 2-bit i/o port with individually configurable pins. port 3 pins are accessed directly by writing or reading the port 3 data register, p3 at location e7h in page 0. p3.0-p3.1 can serve as inputs (with or without pull- up, and high impedance input), as outputs (push-pull or open-drain) or you can be configured the following functions. ? low-nibble pins (p3.0-p3.1): seg2-seg3, intp port 3 control register (p3con) port 3 has a 8-bit control register: p3con for p3.0-p3.1. a reset clears the p3con register to "00h", configuring pins to input mode. you use control register setting to select input or output mode (push-pull or open-drain). port 3 pull-up resistor control register (p3pur) using the port 3 pull-up resistor control register, p3pur (f6h, page 0), you can configure pull-up resistors to individually port 3 pins. port 3 interrupt enable, pending, and edge selection registers(p3int, intpnd2.5-.4, p3edge) to process external interrupts at the port 3 pins, three additional control registers are provided: the port 3 interrupt enable register p3int (f7h, page 0), the port 3 interrupt pending bits intpnd2.5-.4 (d7h, page 0), and the port 3 interrupt edge selection register p3edge (f8h, page 0). the port 3 interrupt pending register bits lets you check for interrupt pending conditions and clear the pending condition when the interrupt service routine has been initiated. the application program detects interrupt requests by polling the intpnd2.5-.4 register at regular intervals. when the interrupt enable bit of any port 3 pin is "1", a rising or falling edge at that pin will generate an interrupt request. the corresponding intpnd2 bit is then automatically set to "1" and the irq level goes low to signal the cpu that an interrupt request is waiting. when the cpu acknowledges the interrupt request, application software must the clear the pending condition by writing a "0" to the corresponding intpnd2 bit. port 3 control register (p3con) f5h, page 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb not used p3.1/seg2 (intp) p3.0/seg3 (intp) p3con bit-pair pin configuration settings: 00 01 10 11 n-channel open-drain output mode not available push-pull output mode schmitt trigger input mode figure 9-14. port 3 control register (p3con)
i/o ports s3c9228/p 9228 9- 12 port 3 interrupt control register (p3int) f7h, page 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb not used p3int bit configuration settings: 0 1 enable interrupt disable interrupt p3.1 (intp) p3.0 (intp) figure 9-15. port 3 interrupt control register (p3int) port 3 interrupt pending bits (intpnd2.5-.4) d7h, page 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb intpnd2 bit configuration settings: 0 1 interrupt is pending (when read) no interrupt pending (when read), clear pending bit (when write) timer 1/a not used timer b sio watch timer p3.0 (intp) p3.0 (intp) figure 9-16. port 3 interrupt pending bits (intpnd2.5-.4)
s3c9228/p9228 i/o p orts 9- 13 port 3 interrupt edge selection register (p3edge) f8h, page 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p3edge bit configuration settings: 0 1 rising edge detection falling edge detection p3.1 (intp) p3.0 (intp) not used figure 9-17. port 3 interrupt edge selection register (p3edge) port 3 pull-up control register (p3pur) f6h, page 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p3pur bit configuration settings: 0 1 enable pull-up resistor disable pull-up resistor not used p3.1 p3.0 figure 9-18. port 3 pull-up control register (p3pur)
i/o ports s3c9228/p 9228 9- 14 port 4 port 4 is an 8-bit i/o port with individually configurable pins. port 4 pins are accessed directly by writing or reading the port 4 data register, p4 at location e8h in page 0. p4.0-p4.7 can serve as inputs or as push-pull, open-drain outputs. you can configure the following alternative functions with lcd port control register, lpot: ? low-nibble pins (p4.0-p4.3): seg4-seg7 ? high-nibble pins (p4.4-p4.7): seg8-seg11 port 4 control registers (p4conh, p4conl) port 4 has two 8-bit control registers: p4conh for p4.4-p4.7 and p4conl for p4.0-p4.3. a reset clears the p4conh and p4conl registers to "00h", configuring all pins to input mode. you use control registers setting to select input or output mode. port 4 control register, high byte (p4conh) f9h, page 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p4.5/seg9 p4.4/seg8 p4conh bit-pair pin configuration settings: 00 01 10 11 n-channel open-drain output mode input mode with pull-up push-pull output mode input mode p4.6/seg10 p4.7/seg11 figure 9-19. port 4 high-byte control register (p4conh) port 4 control register, low byte (p4conl) fah, page 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p4.1/seg5 p4.0/seg4 p4conl bit-pair pin configuration settings: 00 01 10 11 n-channel open-drain output mode input mode with pull-up push-pull output mode input mode p4.2/seg6 p4.3/seg7 figure 9-20. port 4 low-byte control register (p4conl)
s3c9228/p9228 i/o p orts 9- 15 port 5 port 5 is an 8-bit i/o port with individually configurable pins. port 5 pins are accessed directly by writing or reading the port 5 data register, p5 at location e9h in page 0. p5.0-p5.7 can serve as inputs or as push-pull, open-drain outputs. you can configure the following alternative functions with lcd port control register, lpot: ? low-nibble pins (p5.0-p5.3): seg12-seg15 ? high-nibble pins (p5.4-p5.7): seg16-seg19, com4-com7 port 5 control registers (p5conh, p5conl) port 5 has two 8-bit control registers: p5conh for p5.4-p5.7 and p4conl for p5.0-p5.3. a reset clears the p5conh and p5conl registers to "00h", configuring all pins to input mode. you use control registers setting to select input or output mode. port 5 control register, high byte (p5conh) fbh, page 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p5.5/seg17/com6 p5.4/seg16/com7 p5conh bit-pair pin configuration settings: 00 01 10 11 n-channel open-drain output mode input mode with pull-up push-pull output mode input mode p5.6/seg18/com5 p5.7/seg19/com4 figure 9-21. port 5 high-byte control register (p5conh) port 5 control register, low byte (p5conl) fch, page 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p5.1/seg13 p5.0/seg12 p5conl bit-pair pin configuration settings: 00 01 10 11 n-channel open-drain output mode input mode with pull-up push-pull output mode input mode p5.2/seg14 p5.3/seg15 figure 9-22. port 5 low-byte control register (p5conl)
i/o ports s3c9228/p 9228 9- 16 port 6 port 6 is an 4-bit i/o port with individually configurable pins. port 6 pins are accessed directly by writing or reading the port 6 data register, p6 at location eah in page 0. p6.0-p6.3 can serve as inputs or as push-pull, open-drain outputs. you can configure the following alternative functions with lcd port control register, lpot: ? low-nibble pins (p6.0-p6.3): com0-com3 port 6 control register (p6con) port 6 has a 8-bit control register: p6conh for p6.0-p6.3. a reset clears the p6con registers to "00h", configuring all pins to input mode. you use control registers setting to select input or output mode. port 6 control register, low byte (p6con) fdh, page 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p6.1/com2 p6.0/com3 p6con bit-pair pin configuration settings: 00 01 10 11 n-channel open-drain output mode input mode with pull-up push-pull output mode input mode p6.2/com1 p6.3/com0 figure 9-23. port 6 control register (p6con)
s3c9228/p9228 ( preliminary spec ) basic timer 10- 1 10 basic timer overview basic timer (bt) can be used in two different ways: ? as a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction. ? to signal the end of the required oscillation stabilization interval after a reset or a stop mode release. the functional components of the basic timer block are: ? clock frequency divider ( f xx divided by 4096, 1024, 128, or 16) with multiplexer ? 8-bit basic timer counter, btcnt (ddh, read-only) ? basic timer control register, btcon (dch, read/write)
basic timer s3c9228 /p9228 ( preliminary spec ) 10- 2 basic timer control register (btcon) the basic timer control register, btcon, is used to select the input clock frequency, to clear the basic timer counter and frequency dividers, and to enable or disable the watchdog timer function. it is located in page 0, address dch, and is read/write addressable using register addressing mode. a reset clears btcon to "00h". this enables the watchdog function and selects a basic timer clock frequency of f xx /4096. to disable the watchdog function, you must write the signature code ?1010b? to the basic timer register control bits btcon.7?btcon.4. the 8-bit basic timer counter, btcnt (page 0, ddh), can be cleared at any time during normal operation by writing a "1" to btcon.1. to clear the frequency dividers for the basic timer input clock and timer counters, you write a "1" to btcon.0. basic timer control register (btcon) dch, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb divider clear bit for basic timer and timer counters: 0 = no effect 1 = clear divider basic timer counter clear bit: 0 = no effect 1 = clear btcnt basic timer input clock selection bits: 00 = f xx /4096 01 = f xx /1024 10 = f xx /128 11 = f xx /16 watchdog function enable bits: 1010b other value = disable watchdog timer = enable watchdog timer figure 10-1. basic timer control register (btcon)
s3c9228/p9228 ( preliminary spec ) basic timer 10- 3 basic timer function description watchdog timer function you can program the basic timer overflow signal (btovf) to generate a reset by setting btcon.7?btcon.4 to any value other than ?1010b?. (the ?1010b? value disables the watchdog function.) a reset clears btcon to ?00h?, automatically enabling the watchdog timer function. a reset also selects the cpu clock (as determined by the current clkcon register setting), divided by 4096, as the bt clock. a reset whenever a basic timer counter overflow occurs. during normal operation, the application program must prevent the overflow, and the accompanying reset operation, from occurring. to do this, the btcnt value must be cleared (by writing a "1" to btcon.1) at regular intervals. if a system malfunction occurs due to circuit noise or some other error condition, the bt counter clear operation will not be executed and a basic timer overflow will occur, initiating a reset. in other words, during normal operation, the basic timer overflow loop (a bit 7 overflow of the 8-bit basic timer counter, btcnt) is always broken by a btcnt clear instruction. if a malfunction does occur, a reset is triggered automatically. oscillation stabilization interval timer function you can also use the basic timer to program a specific oscillation stabilization interval following a reset or when stop mode has been released by an external interrupt. in stop mode, whenever a reset or an internal and an external interrupt occurs, the oscillator starts. the btcnt value then starts increasing at the rate of fxx/4096 (for reset), or at the rate of the preset clock source (for an internal and an external interrupt). when btcnt.3 overflows, a signal is generated to indicate that the stabilization interval has elapsed and to gate the clock signal off to the cpu so that it can resume normal operation. in summary, the following events occur when stop mode is released: 1. during stop mode, a power-on reset or an internal and an external interrupt occurs to trigger the stop mode release and oscillation starts. 2. if a power-on reset occurred, the basic timer counter will increase at the rate of fx x /4096. if an internal and an external interrupt is used to release stop mode, the btcnt value increases at the rate of the preset clock source. 3. clock oscillation stabilization interval begins and continues until bit 3 of the basic timer coun ter overflows. 4. when a btcnt.3 overflow occurs, normal cpu operation resumes.
basic timer s3c9228 /p9228 ( preliminary spec ) 10- 4 note: during a power-on reset operation, the cpu is idle during the required oscillation stabilization interval (until bit 4 of the basic timer counter overflows). mux f xx /4096 div f xx /1024 f xx /128 f xx /16 f xx bits 3, 2 bit 0 basic timer control register (write '1010xxxxb' to disable) clear bit 1 reset or stop data bus 8-bit up counter (btcnt, read-only) start the cpu (note) ovf reset r figure 10-2. basic timer block diagram
s3c9228/p9228 timer 1 11- 1 11 timer 1 one 16-bit timer mode (timer 1) the 16-bit timer 1 is used in one 16-bit timer or two 8-bit timers mode. if tacon.7 is set to "1", timer 1 is used as a 16-bit timer. if tacon.7 is set to "0", timer 1 is used as two 8-bit timers. ? one 16-bit tim er mode (timer 1) ? two 8-bit timers mode (timer a and b) overview the 16-bit timer 1 is an 16-bit general-purpose timer. timer 1 has the interval timer mode by using the appropriate tacon setting. timer 1 has the following functional components: ? clock frequency divider ( fxx divided by 512, 256, 64, 8, or 1, fxt, and t1clk: external clock) with multiplexer ? 16-bit counter (tacnt, tbcnt), 16-bit comparator, and 16-bit reference data register (tadata, tbdata) ? timer 1 match interrupt generation ? timer 1 control register, tacon (page 0, bbh, read/write) function description interval timer function the timer 1 module can generate an interrupt: the timer 1 match interrupt (t1int). the t1int pending condition should be cleared by software when it has been serviced. even though t1int is disabled, the application's service routine can detect a pending condition of t1int by the software and execute it's sub-routine. when this case is used, the t1int pending bit must be cleared by the application sub-routine by writing a "0" to the intpnd2.0 pending bit. in interval timer mode, a match signal is generated when the counter value is identical to the values written to the timer 1 reference data registers, tadata and tbdata. the match signal generates a timer 1 match interrupt and clears the counter. if, for example, you write the value 32h and 10h to tadata and tbdata, respectively, and 8eh to tacon, the counter will increment until it reaches 3210h. at this point, the timer 1 interrupt request is generated, the counter value is reset, and counting resumes.
timer 1 s3c9228/p922 8 11- 2 timer 1 control register (tacon) you use the timer 1 control register, tacon, to ? enable the timer 1 operating (interval timer) ? select the timer 1 input clock frequency ? clear the timer 1 counter, tacnt and tbcnt ? enable the timer 1 interrupt tacon is located in page 0, at address bbh, and is read/write addressable using register addressing mode. a reset clears tacon to "00h". this sets timer 1 to disable interval timer mode, selects an input clock frequency of fxx/512, and disables timer 1 interrupt. you can clear the timer 1 counter at any time during normal operation by writing a "1" to tacon.3. to enable the timer 1 interrupt, you must write tacon.7, tacon.2, and tacon.1 to "1". to generate the exact time interval, you should write tacon.3 and intpnd2.0, which cleared counter and interrupt pending bit. to detect an interrupt pending condition when t1int is disabled, the application program polls pending bit, intpnd.2.0. when a "1" is detected, a timer 1 interrupt is pending. when the t1int sub- routine has been serviced, the pending condition must be cleared by software by writing a "0" to the timer 1 interrupt pending bit, intpnd2.0. timer a control register (tacon) bbh, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb timer 1/a interrupt enable bit: 0 = disable interrupt 1 = enable interrupt not used timer 1/a counter enable bit: 0 = disable counting operation 1 = enable counting operation timer 1/a counter clear bit: 0 = no affect 1 = clear the timer 1/a counter (when write) one 16-bit timer or two 8-bit timers mode: 0 = two 8-bit timers mode (timer a/b) 1 = one 16-bit timer mode (timer 1) timer 1/a clock selection bits: 000 = fxx/512 001 = fxx/256 010 = fxx/64 011 = fxx/8 100 = fxx 101 = fxt (sub clock) 110 = t1clk (external clock) 111 = not available figure 11-1. timer 1 control register (tacon)
s3c9228/p9228 timer 1 11- 3 note: when one 16-bit timer mode (tacon.7 <- "1": timer 1) tacon.6-.4 m u x 1/8 1 /64 1 /256 1 /512 intpnd2.0 taout t1int 1/1 div r fxt t1clk (x in or xt in ) fxx btcon.0 tacon.2 tbcnt tacnt 16-bit comparator tbdata buffer tadata buffer tbdata tadata lsb msb lsb msb match signal counter clear signal tacon.1 match r tacon.3 data bus data bus clear figure 11-2. timer 1 block diagram (one 16-bit mode)
timer 1 s3c9228/p922 8 11- 4 two 8-bit timers mode (timer a and b) overview the 8-bit timer a and b are the 8-bit general-purpose timers. timer a and b have the interval timer mode by using the appropriate tacon and tbcon setting, respectively. timer a and b have the following functional components: ? clock frequency divider with multiplexer ? fxx divided by 512, 256, 64, 8 or 1, fxt, and t1clk (external clock) for timer a ? fxx divided by 512, 256, 64, 8 or 1, and fxt for timer b ? 8-bit counter (tacnt, tbcnt), 8-bit comparator, and 8-bit reference data register (tadata, tbdata) ? timer a have i/o pin for match output (taout) ? timer a match interrupt generation ? timer a control register, tacon (pag e 0, bbh, read/write) ? timer b match interrupt generation ? timer b control register, tbcon (page 0, bah, read/write) timer a and b control register (tacon, tbcon) you use the timer a and b control register, tacon and tbcon, to ? enable the timer a (interval timer mode) and b operating (interval timer mode) ? select the timer a and b input clock frequency ? clear the timer a and b counter, tacnt and tbcnt ? enable the timer a and b interrupt
s3c9228/p9228 timer 1 11- 5 tacon and tbcon are located in page 0, at address bbh and bah, and is read/write addressable using register addressing mode. a reset clears tacon to "00h". this sets timer a to disable interval timer mode, selects an input clock frequency of fxx/512, and disables timer a interrupt. you can clear the timer a counter at any time during normal operation by writing a "1" to tacon.3. a reset clears tbcon to "00h". this sets timer b to disable interval timer mode, selects an input clock frequency of fxx/512, and disables timer a interrupt. you can clear the timer b counter at any time during normal operation by writing a "1" to tbcon.3. to enable the timer a interrupt (taint) and timer b interrupt (tbint), you must write tacon.7 to "0", tacon.2 (tbcon.2) and tacon.1 (tbcon.1) to "1". to generate the exact time interval, you should write tacon.3 (tbcon.3) and intpnd2.0 (intpnd2.1), which cleared counter and interrupt pending bit. to detect an interrupt pending condition when taint and tbint is disabled, the application program polls pending bit, intpnd2.0 and intpnd2.1. when a "1" is detected, a timer a interrupt (taint) and timer b interrupt (tbint) is pending. when the taint and tbint sub-routine has been serviced, the pending condition must be cleared by software by writing a "0" to the timer a and b interrupt pending bit, intpnd2.0 and intpnd2.1. timer a control register (tacon) e4h, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb timer a interrupt enable bit: 0 = disable interrupt 1 = enable interrupt not used timer a counter enable bit: 0 = disable counting operation 1 = enable counting operation timer a counter clear bit: 0 = no affect 1 = clear the timer a counter (when write) one 16-bit timer or two 8-bit timers mode: 0 = two 8-bit timers mode (timer a/b) 1 = one 16-bit timer mode (timer 1) timer a clock selection bits: 000 = fxx/512 001 = fxx/256 010 = fxx/64 011 = fxx/8 100 = fxx 101 = fxt (sub clock) 110 = t1clk (external clock) 111 = not available figure 11-3. timer a control register (tacon)
timer 1 s3c9228/p922 8 11- 6 timer b control register (tbcon) bah, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb timer b match interrupt enable bit: 0 = disable match interrupt 1 = enable match interrupt not used timer b count enable bit: 0 = disable counting operating 1 = enable counting operating timer b counter clear bit: 0 = no effect 1 = clear the timer b counter (when write) timer b clock selection bits: 000 = f x x/512 001 = f x x/256 010 = f x x/64 011 = fxx/8 100 = fxx (system clock) 101 = fxt (sub clock) 110 = not available 111 = not available not used figure 11-4. timer b control register (tbcon)
s3c9228/p9228 timer 1 11- 7 function description interval timer function (timer a and timer b) the timer a and b module can generate an interrupt: the timer a match interrupt (taint) and the timer b match interrupt (tbint). the timer a match interrupt pending condition (intpnd2.0) and the timer b match interrupt pending condition (intpnd2.1) must be cleared by software in the application's interrupt service by means of writing a "0" to the intpnd2.0 and intpnd2.1 interrupt pending bit. even though taint and tbint are disabled, the application's service routine can detect a pending condition of taint and tbint by the software and execute it's sub-routine. when this case is used, the taint and tbint pending bit must be cleared by the application sub-routine by writing a "0" to the corresponding pending bit intpnd2.0 and intpnd2.1. in interval timer mode, a match signal is generated when the counter value is identical to the values written to the timer a or timer b reference data registers, tadata or tbdata. the match signal generates corresponding match interrupt and clears the counter. if, for example, you write the value 20h to tadata and 0eh to tacon, the counter will increment until it reaches 20h. at this point, the timer a interrupt request is generated, the counter value is cleared, and counting resumes and you write the value 10h to tbdata, "0" to tacon.7, and 0eh to tbcon, the counter will increment until it reaches 10h. at this point, tb interrupt request is generated, the counter value is cleared and counting resumes.
timer 1 s3c9228/p922 8 11- 8 note: when two 8-bit timers mode (tacon.7 <- "0": timer a) tacon.6-.4 m u x 1/8 1 /64 1 /256 1 /512 intpnd2.0 taout taint div r fxt t1clk/ p0.1 (x in or xt in ) fxx btcon.0 tacon.2 8-bit comparator tadata buffer tadata register lsb msb lsb msb match signal counter clear signal tacon.1 match r tacon.3 data bus data bus tacnt (8-bit up-counter) clear 1/1 figure 11-5. timer a block diagram(two 8-bit timers mode)
s3c9228/p9228 timer 1 11- 9 1/1 1/8 1 /64 1 /256 1 /512 note: when two 8-bit timers mode (tacon.7 <- "0": timer b) tbcon.6-.4 m u x intpnd2.1 tbint div r fxt (x in or xt in ) fxx btcon.0 tbcon.2 8-bit comparator tbdata buffer tbdata register lsb msb lsb msb match signal counter clear signal tbcon.1 match r tbcon.3 data bus data bus tbcnt (8-bit up-counter) clear figure 11-6. timer b block diagram (two 8-bit timers mode)
timer 1 s3c9228/p922 8 11- 10 notes
s3c9228/p9228 watch timer 12- 1 12 watch timer overview watch timer functions include real-time and watch-time measurement and interval timing for the system clock. to start watch timer operation, set bit 1 of the watch timer control register, wtcon.1 to "1". and if you want to service watch timer overflow interrupt, then set the wtcon.6 to ?1?. the watch timer overflow interrupt pending condition (intpnd2.3) must be cleared by software in the application's interrupt service routine by means of writing a "0" to the intpnd2.3 interrupt pending bit. after the watch timer starts and elapses a time, the watch timer interrupt pending bit (intpnd2.3) is automatically set to "1", and interrupt requests commence in 3.91ms, 0.25, 0.5 and 1-second intervals by setting watch timer speed selection bits (wtcon.3 ? .2). the watch timer can generate a steady 0.5 khz, 1 khz, 2 khz, or 4 khz signal to buz output pin for buzzer. by setting wtcon.3 and wtcon.2 to "11b", the watch timer will function in high-speed mode, generating an interrupt every 3.91 ms. high-speed mode is useful for timing events for program debugging sequences. also, you can select watch timer clock source by setting the wtcon.7 appropriately value. the watch timer supplies the clock frequency for the lcd controller (f lcd ). therefore, if the watch timer is disabled, the lcd controller does not operate. watch timer has the following functional components: ? real time and watch-time measurement ? using a main or sub clock source (main clock divided by 2 7 (fx/128) or sub clock( fxt)) ? clock source generation for lcd controller (f lcd ) ? i/o pin for buzzer output frequency generator (p0.3, buz) ? timing tests in high-speed mode ? watch timer overflow interrupt generation ? watch timer control regi ster, wtcon (page 0, dah, read/write)
watch timer s3c922 8/p9228 12- 2 watch timer control register (wtcon) the watch timer control register, wtcon is used to select the input clock source, the watch timer interrupt time and buzzer signal, to enable or disable the watch timer function. it is located in page 0 at address dah, and is read/write addressable using register addressing mode. a reset clears wtcon to "00h". this disable the watch timer and select fx/128 as the watch timer clock. so, if you want to use the watch timer, you must write appropriate value to wtcon. buzzer signal selection bits: 00 = 0.5 khz 01 = 1 khz 10 = 2 khz 11 = 4 khz watch timer control register (wtcon) dah, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb watch timer enable/disable bit: 0 = disable watch timer; clear frequency dividing circuits 1 = enable watch timer not used watch timer speed selection bits: 00 = set watch timer interrupt to 1 s 01 = set watch timer interrupt to 0.5 s 10 = set watch timer interrupt to 0.25 s 11 = set watch timer interrupt to 3.91 ms watch timer clock selection bit: 0 = main clock divided by 2 7 (fx/128) 1 = sub clock (fxt) watch timer int enable/disable bit: 0 = disable watch timer int 1 = enable watch timer int figure 12-1. watch timer control register (wtcon)
s3c9228/p9228 watch timer 12- 3 watch timer circuit diagram wt int enable wtcon.1 wtcon.2 wtcon.3 wtcon.4 wtcon.5 wtcon.6 enable/disable selector circuit mux intpnd2.3 wtint wtcon.6 f w /2 15 f w /2 14 f w /2 13 f w /2 7 f w /64 (0.5 khz) f w /32 (1 khz) f w /16 (2 khz) f w /8 (4 khz) (1 hz) f x = main clock (where fx = 4.19 mhz) fxt = sub clock (32,768 hz) f w = watch timer frequency clock selector frequency dividing circuit f w 32.768 khz f xt f lcd = 2048 hz wtcon.7 wtcon.0 8 buz (p0.3) fx/128 figure 12-2. watch timer circuit diagram
watch timer s3c922 8/p9228 12- 4 notes
s3c9228/p9228 lcd controller/driv er 13- 1 1 3 lcd controller/driv er overview the s3c9228/p9228 microcontroller can directly drive an up-to- 128 -dot ( 16 segments x 8 commons) lcd panel. its lcd block has the following components: ? lcd control ler/driver ? display ram for storing display data ? 16 segment output pins (seg0 ? seg 15 ) ? 8 common output pins (com0? com7 ) ? internal resistor circuit for lcd bias to use the lcd controller, bit 2 in the watch mode register wmod must be set to 1 because lcdck is supplied by the watch timer. the lcd mode control register, l mod , is used to turn the lcd display on or off, to s elect lcd clock frequency, to turn the com signal output on or off, to select bias and duty, and to switch the port 3 high impedance or normal i/o port . data written to the lcd display ram can be transferred to the segment signal pins automatically without program control. the lcd port control register, lpot, is used to determine the lcd signal pins used for display output. when a sub clock is selected as the lcd clock source, the lcd display is enabled even during main clock stop and idle modes. lcd controller/ driver com0-com3 seg0/p2.1- seg15/p5.3 16 4 8 data bus com4/seg19- com7/seg16 4 figure 13- 1. lcd function diagram
lcd controller/driver s3c9228/p9228 13- 2 lcd circuit diagram seg15/p5.3 com4/seg19/p5.7 com7/seg16/p5.4 160 16 data bus port latch lpot display ram (page1) port latch port latch timing controller mux seg control or selector com control or selector f lcd seg0/p2.1 com3/p6.0 com0/p6.3 com control lcd voltage control port 3 control p3.1/intp/seg2 p3.0/intp/seg3 lmod 16 4 8 2 figure 13- 2. lcd circuit diagram
s3c9228/p9228 lcd controller/driv er 13- 3 lcd ram address area ram addresses of page 1 are used as lcd data memory. when the bit value of a display segment is "1", the lcd display is turned on; when the bit value is "0", the display is turned off. display ram data are sent out through segment pins seg0?seg 19 using a direct memory access (dma) method that is synchronized with the f lcd signal. ram addresses in this location that are not used for lcd display can be allocated to general-purpose use. com0 com1 com2 com3 b0 b1 b2 b3 b4 b5 b6 b7 seg0 com7 com6 com5 com4 seg1 seg2 seg3 100h 101h 102h 103h 111h 112h 113h seg17 seg18 seg19 figure 13- 3. lcd display data ram organization table 13- 1. common and segment pins per duty cycle duty common pins segment pins dot number 1/ 8 com0?com 7 16 pins 128 dots 1/4 com0? com3 20 pins 80 dots 1/3 com0?com 2 20 pins 60 dots
lcd controller/driver s3c9228/p9228 13- 4 lcd mode control register (lmod) a lmod is located in page 0, at address feh, and is read/write addressable using register addressing mode. it has the following control functions. ? lcd duty and bias selection ? lcd clock selection ? lcd display control ? coms signal output control ? p3 high impedance control the lmod register is used to turn the lcd display on/off, to select duty and bias, to select lcd clock, to control port 3 high impedance/normal i/o port, and to turn the com signal output on/off. following a reset , all lmod values are cleared to "0". this turns off the lcd display, select 1/3 duty and 1/3 bias, and select 256hz for lcd clock. the lcd clock signal determines the frequency of com signal scanning of each segment output. this is also referred as the lcd frame frequency. since the lcd clock is generated by watch timer clock ( fw). the watch timer should be enabled when the lcd display is turned on. lcd mode control register (lmod) feh, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb not used lcd duty and bias selection bits: 00 = 1/3 duty, 1/3 bias (com0-com2, seg0-seg19) 01 = 1/4 duty, 1/3 bias (com0-com3, seg0-seg19) 10 = 1/8 duty, 1/4 bias (com0-com7, seg0-seg15) 11 = 1/8 duty, 1/5 bias (com0-com7, seg0-seg15) com pins high impedance control bit: 0 = normal coms signal output 1 = high impendane com pins lcd clock selection bits: 00 = fw/2 7 (256 hz when fw is 32.768 khz) 01 = fw/2 6 (512 hz when fw is 32.768 khz) 10 = fw/2 5 (1024 hz when fw is 32.768 khz) 11 = fw/2 4 (2048 hz when fw is 32.768 khz) port 3 high impendance control bit 0 = normal i/o 1 = high impendane input lcd display control bit 0 = display off 1 = normal display on figure 13-4. lcd mode control register (lmod)
s3c9228/p9228 lcd controller/driv er 13- 5 lcd port control register the lcd port control register lpot is used to control lcd signal pins or normal i/o pins. following a reset , a lpot values are cleared to "0". lcd port control register d8h, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb not used seg0/p2.1 selection bit: 0 = seg port 1 = normal i/o port seg4-seg19 and com0-com3 selection bits: 000 = p4.0-p6.3: lcd signal pins 001 = p4.0-p4.3: normal i/o, p4.4-p6.3: lcd signal pins 010 = p4.0-p4.7: normal i/o, p5.0-p6.3: lcd signal pins 011 = p4.0-p5.3: normal i/o, p5.4-p6.3: lcd signal pins 100 = p4.0-p5.7: normal i/o, p6.0-p6.3: lcd signal pins 101 = p4.0-p6.3: normal i/o 110 = not available 111 = not available seg1/p2.0 selection bit: 0 = seg port 1 = normal i/o port seg2/p3.1 selection bit: 0 = seg port 1 = normal i/o port seg3/p3.0 selection bit: 0 = seg port 1 = normal i/o port figure 13-5. lcd port control register
lcd controller/driver s3c9228/p9228 13- 6 lcd voltage dividing resistors 1/5 bias s3c9228/p9228 v dd r r r r r lmod.4 v lc1 v lc2 v lc3 v lc4 v lc5 v ss 1/4 bias s3c9228/p9228 v dd r r r r r lmod.4 v lc1 v lc2 v lc3 v lc4 v lc5 v ss 1/3 bias s3c9228/p9228 v dd r r r r r lmod.4 v lc1 v lc2 v lc3 v lc4 v lc5 v ss figure 13-6. internal voltage dividing resistor connection common (com) signals the common signal output pin selection (com pin selection) varies according to the selected duty cycle. ? in 1/3 duty mode, com0-com2 pins are selected ? in 1/4 duty mode, com0-com3 pins are selected ? in 1/8 duty mode, com0-com7 pins are selected segment (seg) signals the 19 lcd segment signal pins are connected to corresponding display ram locations at page 1. bits of the display ram are synchronized with the common signal output pins. when the bit value of a display ram location is "1", a select signal is sent to the corresponding segment pin. when the display bit is "0", a 'no-select' signal to the corresponding segment pin.
s3c9228/p9228 lcd controller/driv er 13- 7 1 frame fr v dd v ss com0 com1 com2 com3 com4 com5 com6 com7 com1 v lc2 (v lc3 ) v lc4 v ss v dd v lc1 seg0 v lc2 (v lc3 ) v lc4 v ss v dd v lc1 com2 v lc2 (v lc3 ) v lc4 v ss v dd v lc1 com0 v lc2 ( v lc3 ) v lc4 v ss v dd v lc1 seg0-com0 + v dd 0v + 1/4v lcd -v lcd - 1/4v lcd 0 1 2 3 7 4 6 5 0 1 2 3 7 4 6 5 s e g 0 s e g 1 s e g 2 s e g 3 s e g 4 figure 13-7 . lcd signal waveforms (1/ 8 duty, 1/ 4 bias)
lcd controller/driver s3c9228/p9228 13- 8 1 frame v dd v ss 0 1 2 3 0 1 2 3 com1 v ss v dd v lc1 ( v lc2 ) v lc3 ( v lc4 ) com2 v ss v dd v lc1 ( v lc2 ) v lc3 ( v lc4 ) com3 v ss v dd v lc1 ( v lc2 ) v lc3 ( v lc4 ) seg0 v ss v dd v lc1 ( v lc2 ) v lc3 ( v lc4 ) seg1 v ss v dd v lc1 ( v lc2 ) v lc3 ( v lc4 ) com0-seg0 + v lcd com0 v ss v dd v lc1 ( v lc2 ) v lc3 ( v lc4 ) + 1/3 v lcd 0v - 1/3 v lcd - v lcd com0 com1 com2 com3 seg1 seg0 figure 13-8. lcd signal waveforms (1/4 duty, 1/ 3 bias)
s3c9228/p9228 lcd controller/driv er 13- 9 1 frame v dd v ss 0 1 2 com1 v ss v dd v lc1 ( v lc2 ) v lc3 ( v lc4 ) com2 v ss v dd v lc1 ( v lc2 ) v lc3 ( v lc4 ) seg0 v ss v dd v lc1 ( v lc2 ) v lc3 ( v lc4 ) seg1 v ss v dd v lc1 ( v lc2 ) v lc3 ( v lc4 ) com0-seg0 + v lcd com0 v ss v dd v lc1 ( v lc2 ) v lc3 ( v lc4 ) + 1/3 v lcd 0v - 1/3 v lcd - v lcd com0 com1 com2 seg2 seg1 seg0 0 1 2 figure 13-9 . lcd signal waveforms (1/ 3 duty, 1/ 3 bias)
lcd controller/driver s3c9228/p9228 13- 10 notes
s3c9228/p9228 a/d c onverter 14- 1 14 10-bit analog-to-digital converter overview the 10-bit a/d converter (adc) module uses successive approximation logic to convert analog levels entering at one of the four input channels to equivalent 10 -bit digital values. the an alog input level must lie between the av ref and av ss values. the a/d converter has the following components: ? analog comparator with successive approximation logic ? d/a converter logic (resistor string type) ? adc control register (adcon) ? four multiplexed analog data input pins (ad0?ad3) ? 10-bit a/d conversion data output register (addatah/addatal) ? 4 -bit digital input port (alternately, i/o port) function description to initiate an analog-to-digital conversion procedure, at first you must set with alternative function for adc input enable at port 1, the pin set with alternative function can be used for adc analog input. and you write the channel selection data in the a/d converter control register adcon.4?.5 to select one of the four analog input pins (ad0?3) and set the conversion start or enable bit, adcon.0. the read-write adcon register is located in page 0, at address d0h. the pins which are not used for adc can be used for normal i/o. during a normal conversion, adc logic initially sets the successive approximation register to 800h (the approximate half-way point of an 10 -bit register). this register is then updated automatically during each conversion step. the successive approximation block performs 10-bit conversions for one input channel at a time. you can dynamically select different channels by manipulating the channel selection bit value (adcon.5? 4) in the adcon register. to start the a/d conversion, you should set the enable bit, adcon.0. when a conversion is completed, adcon.3, the end-of-conversion(eoc) bit is automatically set to 1 and the result is dumped into the addatah/addatal register where it can be read. the a/d converter then enters an idle state. remember to read the contents of addatah/addatal before another conversion starts. otherwise, the previous result will be overwritten by the next conversion result. note because the a/d converter has no sample-and-hold circuitry, it is very important that fluctuation in the analog level at the ad0?ad3 input pins during a conversion procedure be kept to an absolute minimum. any change in the input level, perhaps due to noise, will invalidate the result. if the chip enters to stop or idle mode in conversion process, there will be a leakage current path in a/d block. you must use stop or idle mode after adc operation is finished.
a/d converter s3c9 228/p9228 14- 2 conversion timing the a/d conversion process requires 4 steps (4 clock edges) to convert each bit and 10 clocks to set-up a/d conversion. therefore, total of 50 clocks are required to complete an 10-bit conversion: when fxx/8 is selected for conversion clock with an 4.5 mhz fxx clock frequency, one clock cycle is 1.78 us. each bit conversion requires 4 clocks, the conversion rate is calculated as follows: 4 clocks/bit 10-bit + set-up time = 50 clocks, 50 clock 1.78 us = 89 us at 0.56 mhz (4.5 mhz/8) note that a/d converter needs at least 25 m s for conversion time. a/d converter control register (adcon) the a/d converter control register, adcon, is located at address d0h in page 0. it has three functions: ? analog input pin selection (bits 4 and 5) ? end-of-conversion status detection (bit 3) ? adc clock selection (bits 2 and 1) ? a/d operation start or enable (bit 0 ) after a reset, the start bit is turned off. you can select only one analog input channel at a time. other analog input pins (ad0?ad3) can be selected dynamically by manipulating the adcon.4?5 bits. and the pins not used for analog input can be used for normal i/o function. start or enable bit 0 = disable operation 1 = start operation (automatically disable the operation after conversion completes.) a/d converter control register (adcon) d0h, page0, r/w (eoc bit is read-only) .7 .6 .5 .4 .3 .2 .1 .0 msb lsb end-of-conversion bit 0 = not complete conversion 1 = complete conversion always logic zero a/d input pin selection bits: 00 = ad0 01 = ad1 10 = ad2 11 = ad3 clock selection bits: 00 = fxx/16 01 = fxx/8 10 = fxx/4 11 = fxx/1 figure 14-1. a/d converter control register (adcon)
s3c9228/p9228 a/d c onverter 14- 3 conversion data register addatah/addatal d1h/d2h, page 0, read only .9 .8 .7 .6 .5 .4 .3 .2 msb lsb (addatah) - - - - - - .1 .0 msb lsb (addatal) figure 14-2. a/d converter data register (addatah/addatal) internal reference voltage levels in the adc function block, the analog input voltage level is compared to the reference voltage. the analog input level must remain within the range v ss to v dd . different reference voltage levels are generated internally along the resistor tree during the analog conversion process for each conversion step. the reference voltage level for the first conversion bit is always 1/2 v dd . block diagram input pins ad0-ad3 (p1.0-p1.3) clock selector conversion result (addatah/addatal, d1h/d2h, page 0) - + to adcon.3 (eoc flag) successive approximation logic & register v dd v ss analog comparator 10-bit d/a converter m u x adcon.4-5 (select one input pin of the assigned pins) p1con (assign pins to adc input) adcon.0 (ad/c enable) adcon.0 (ad/c enable) . . . adcon.2-.1 figure 14-3. a/d converter functional block diagram
a/d converter s3c9 228/p9228 14- 4 s3c9228 ad0-ad3 analog input pin v dd 101 c (v ss adc input v dd ) figure 14-4. recommended a/d converter circuit for highest absolute accuracy
s3c9228/p9228 serial i/o interface 1 5- 1 1 5 serial i/o interfac e overview serial i/o modules, sio can interface with various types of external device that require serial data transfer. the components of sio function block are: ? 8-bit control register (s iocon ) ? clock selector logic ? 8-bit data buffer (siodata) ? 8-bit prescaler (siops) ? 3-bit serial clock counter ? serial data i/o pins (si, so) ? serial clock input/output pin (sck) the sio module can transmit or receive 8-bit serial data at a frequency determined by its corresponding control register settings. to ensure flexible data transmission rates, you can select an internal or external clock source. programming procedure to program the sio module, follow these basic steps: 1. configure the i/o pins at port (sck/si/so) by loading the appropriate value to the p2con register if necessary. 2. load an 8-bit value to the siocon control register to properly configure the serial i/o module. in this operation, siocon.2 must be set to "1" to enable the data shifter. 3. for interrupt generation, set the serial i/o interrupt enable bit (siocon) to "1". 4. when you transmit data to the serial buffer, write data to siodata and set siocon.3 to 1, the shift operation starts. 5. when the shift operation (transmit/receive) is completed, the sio pending bit (intpnd2.2) are set to "1" and sio interrupt request is generated.
serial i/o interface s3c9228/p9228 15- 2 sio control registers (siocon) the control register for serial i/o interface module, siocon, is located at e1h in page 0. it has the control setting for sio module. ? clock source selection (internal or external) for shift clock ? interrupt enable ? edge selection for shift operation ? clear 3-bit counter and start shift operation ? shift operation (transmit) enable ? mode selection (transmit/receive or receive-only) ? data direction selection (msb first or lsb first) a reset clears the siocon value to "00h". this configures the corresponding module with an internal clock source at the sck, selects receive-only operating mode, and clears the 3-bit counter. the data shift operation and the interrupt are disabled. the selected data direction is msb-first. serial i/o module control register (siocon) e1h, page 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb sio interrupt enable bit: 0 = disable sio interrupt 1 = enable sio interrupt not used sio shift operation enable bit: 0 = disable shifter and clock counter 1 = enable shifter and clock counter shift clock edge selection bit: 0 = t x at falling edeges, rx at rising edges. 1 = t x at rising edeges, rx at falling edges. data direction control bit: 0 = msb-first mode 1 = lsb-first mode sio mode selection bit: 0 = receive only mode 1 = transmit/receive mode sio counter clear and shift start bit: 0 = no action 1 = clear 3-bit counter and start shifting sio shift clock selection bit: 0 = internal clock (p.s clock) 1 = external clock (sck) figure 15- 1. serial i/o module control register (siocon)
s3c9228/p9228 serial i/o interface 1 5- 3 sio pre-scaler register (siops) the prescaler register for serial i/o interface module, siops, are located at e3h in page 0. the value stored in the sio pre-scale register, siops, lets you determine the sio clock rate (baud rate) as follows: baud rate = input clock (fxx/4)/( prescaler value + 1), or sck input clock. sio pre-scaler register (siops) e3h, page 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb baud rate = (f xx /4)/(siops + 1) figure 15-2. sio prescaler register (siops) sio block diagram sio int pending 3-bit counter clear intpnd2.2 fxx /2 siops (e3h, page 0) sck siocon.7 siocon.1 (interrupt enable) clk si siocon.3 data bus so m u x 1/2 8-bit p.s. 8 8-bit sio shift buffer (siodata, e2h, page 0) clk siocon.4 (edge select) siocon.5 (mode select) siocon.2 (shift enable) siocon.6 (lsb/msb first mode select) figure 15-3. sio functional block diagram
serial i/o interface s3c9228/p9228 15- 4 serial i/o timing diagram (sio) so transmit complete sio int set siocon.3 do7 do6 do5 do4 do3 do2 do1 do0 di7 di6 di5 di4 di3 di2 di1 di0 si sck figure 15-4 . serial i/o timing in transmit/receive mode ( tx at falling, siocon.4 = 0) sio int do7 do6 do5 do4 do3 do2 do1 do0 di7 di6 di5 di4 di3 di2 di1 di0 sck transmit complete si so set siocon.3 figure 15-5 . serial i/o timing in transmit/receive mode ( tx at rising, siocon.4 = 1)
s3c9228/p9228 elect rical data 16- 1 16 electrical data overview in this chapter, s3c9228/p9228 electrical characteristics are presented in tables and graphs. the information is arranged in the following order: ? absolute maximum ratings ? d.c. electrical characteristics ? data retention supp ly voltage in stop mode ? stop mode release timing when initiated by an external interrupt ? stop mode release timing when initiated by a reset ? i/o capacitance ? a.c. electrical characteristics ? a/d converter electrical characteristics ? input timing for external interrupt ? input timing for reset ? serial data transfer timing ? oscillation characteristics ? oscillation stabilization time ? operating voltage range
electrical data s3c 9228/p9228 16- 2 table 16-1. absolute maximum ratings (t a = 25 c) parameter symbol conditions rating unit supply voltage v dd ? ? 0.3 to + 6.5 v input voltage v in ports 0 ?6 ? 0.3 to v dd + 0.3 v output voltage v o ? ? 0.3 to v dd + 0.3 v output current high i oh one i/o pin active ? 15 ma all i/o pins active ? 60 output current low i ol one i/o pin active + 30 ma total pin current for ports + 100 operating temperature t a ? ? 25 to + 85 c storage temperature t stg ? ? 65 to + 150 c table 16-2. d.c. electrical characteristics (t a = ? 25 c to + 85 c, v dd = 2.0 v to 5.5 v) parameter symbol conditions min typ max unit operating voltage v dd fx = 0.4?4mhz, fxt = 32.8khz 2.0 ? 5.5 v fx = 0.4?8mhz 2.7 ? 5.5 input high voltage v ih1 ports 4?6 0.7 v dd ? v dd v v ih2 ports 0?3, reset 0.8 v dd v dd v ih3 x in , x out and xt in , xt out v dd ? 0.1 v dd input low voltage v il1 ports 4?6 ? ? 0.3 v dd v v il2 ports 0?3, reset 0.2 v dd v il3 x in , x out , xt in , xt out 0.1 output high voltage v oh v dd = 4.5 to 5.5 v; all output ports; i oh = ?1 ma v dd ? 1.0 ? v dd v output low voltage v ol v dd = 4.5 to 5.5 v; all output ports; i ol = 10 ma ? ? 2.0 v input high leakage current i lih1 v i = v dd ; all input pins except x in , x out , xt in , xt out ? ? 3 m a i lih2 v i = v dd ; x in , x out , xt in , xt out 20
s3c9228/p9228 elect rical data 16- 3 table 16-2. d.c. electrical characteristics (continued) (t a = ? 25 c to + 85 c, v dd = 2.0 v to 5.5 v) parameter symbol conditions min typ max unit input low leakage current i lil1 v i = 0 v; all input pins except reset , x out , xt in , xt out ? ? ?3 m a i lil2 v i = 0 v; x in , x out , xt in , xt out ?20 output high leakage current i loh v o = v dd all output pins ? ? 3 output low leakage current i lol v o = 0 v all output pins ? ? ?3 pull-up resistor r l1 v i = 0 v; v dd = 5v, t a = 25 c ports 0?6 25 47 100 k w v dd = 3v, t a = 25 c 50 90 150 r l2 v i = 0 v; v dd = 5v, t a = 25 c reset 150 250 400 v dd = 3v, t a = 25 c 300 500 700 oscillator feed back resistors r osc1 v dd = 5 v, t a = 25 c x in = v dd , x out = 0v 300 600 1500 k w r osc2 v dd = 5 v, t a = 25 c xt in = v dd , xt out = 0 v 1500 3000 4500 lcd voltage dividing resistor r lcd t a = 25 c 50 70 90 k w ? v lcd - comi ? voltage drop ( i = 0-7) v dc v dd = 2.7 v to 5.5 v - 15 m a per common pin ? ? 120 mv ? v lcd - seg x ? voltage drop (x = 0?19) v ds v dd = 2.7 v to 5.5 v - 15 m a per common pin ? ? 120 middle output voltage v lc2 v dd = 2.7 v to 5.5 v, lcd clock = 0hz, v lc1 = v dd 0.8v dd ?0.2 0.8v dd 0.8v dd + 0.2 v v lc3 0.6v dd ?0.2 0.6v dd 0.6v dd + 0.2 v lc4 0.4v dd ?0.2 0.4v dd 0.4v dd + 0.2 v lc5 0.2v dd ?0.2 0.2v dd 0.2v dd + 0.2 note: low leakage current is absolute value.
electrical data s3c 9228/p9228 16- 4 table 16-2. d.c. electrical characteristics (concluded) (t a = ? 25 c to + 85 c, v dd = 2.0 v to 5.5 v) parameter symbol conditions min typ max unit supply current (1) i dd1 run mode: v dd = 5 v 10% 8.0 mhz ? 6.0 12.0 ma crystal oscillator c1 = c2 = 22pf 4.19 mhz 3.0 6.0 v dd = 3 v 10% 8.0 mhz 2.5 5.0 4.19 mhz 1.5 3.0 i dd2 idle mode: v dd = 5 v 10% 8.0 mhz 1.3 3.0 crystal oscillator c1 = c2 = 22pf 4.19 mhz 1.0 2.0 v dd = 3 v 10% 8.0 mhz 0.8 1.6 4.19 mhz 0.4 0.8 i dd3 run mode: v dd = 3 v 10%, 32 khz crystal oscillator 15 30 m a i dd4 idle mode: v dd = 3 v 10%, 32 khz crystal oscillator 6 15 i dd5 stop mode; v dd = 5 v 10%, t a = 25 c 0.5 3 stop mode; v dd = 3 v 10%, t a = 25 c 0.3 2 notes: 1. supply current does not include current drawn through internal pull-up resistors, lcd voltage dividing resistors, and adc. 2. i dd1 and i dd2 include power consumption for subsystem clock oscillation. 3. i dd3 and i dd4 are current when main system clock oscillation stops and the subsystem clock is used. 4. i dd5 is current when main system clock and subsystem clock oscillation stops.
s3c9228/p9228 elect rical data 16- 5 table 16-3. data retention supply voltage in stop mode (t a = ? 25 c to + 85 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr ? 2.0 ? 5.5 v data retention supply current i dddr stop mode, t a = 25 c v dddr = 2.0 v ? ? 1 a execution of stop instruction idle mode (basic timer active) ~ ~ v dddr ~ ~ stop mode normal operating mode data retention mode v dd 0.8 v dd t wait note: t wait is the same as 16 x 1/bt clock. figure 16-1. stop mode release timing when initiated by an external interrupt
electrical data s3c 9228/p9228 16- 6 execution of stop instrction reset occurs ~ ~ v dddr ~ ~ stop mode oscillation stabilization time normal operating mode data retention mode t wait reset v dd 0.2 v dd 0.8 v dd note: t wait is the same as 16 1/bt clock. figure 16-2. stop mode release timing when initiated by a reset reset table 16-4. input/output capacitance (t a = 25 c, v dd = 0 v) parameter symbol conditions min typ max unit input capacitance c in f = 1 mhz; unmeasured pins are connected to v ss ? ? 10 pf output capacitance c out i/o capacitance c io
s3c9228/p9228 elect rical data 16- 7 table 16-5. a.c. electrical characteristics (t a = ? 25 c to + 85 c, v dd = 2.0 v to 5.5 v) parameter symbol conditions min typ max unit sck cycle time t kcy external sck source 1,000 ? ? ns internal sck source 1,000 sck high, low width t kh , t kl external sck source 500 internal sck source t kcy /2?50 si setup time to sck high t sik external sck source 250 internal sck source 250 si hold time to sck high t ksi external sck source 400 internal sck source 400 output delay for sck to so t kso external sck source ? ? 300 ns internal sck source 250 interrupt input, high, low width t inth , t intl all interrupt v dd = 3 v 500 700 ? ns reset input low width t rsl input v dd = 3 v 10 ? ? m s
electrical data s3c 9228/p9228 16- 8 table 16-6. a/d converter electrical characteristics (t a = ? 25 c to + 85 c, v dd = 2.7 v to 5.5 v, v ss = 0 v) parameter symbol conditions min typ max unit resolution ? 10 ? bit total accuracy vdd = 5.12 v ? ? 3 lsb integral linearity error ile fxx = 8 mhz ? ? 2 differential linearity error dle f con = fxx/4 ? ? 1 offset error of top eot ? 1 3 offset error of bottom eob ? 0.5 2 conversion time (1) t con 10-bit resolution 50 fxx/4, fxx = 8mhz 25 ? ? m s analog input voltage v ian ? v ss ? v dd v analog input impedance r an ? 2 1000 ? m w analog input current i adin v dd = 5 v ? ? 10 m a i adc v dd = 5 v ? 1 3 ma v dd = 3 v 0.5 1.5 v dd = 5 v when power down mode 100 500 na notes: 1. 'conversion time' is the time required from the moment a conversion operation starts until it ends. 2. i adc is an operating current during a/d conversion. t inth t intl 0.8 v dd 0.2 v dd note: the unit t cpu means one cpu clock period. external interrupt figure 16-3. input timing for external interrupts
s3c9228/p9228 elect rical data 16- 9 reset t rsl 0.2 v dd figure 16-4. input timing for reset reset t kh t kl 0.2v dd sck t kcy 0.8v dd 0.8v dd 0.2v dd t sik t ksi si so t kso output data figure 16-5. serial data transfer timing
electrical data s3c 9228/p9228 16- 10 table 16-7. main oscillation characteristics (t a = ? 25 c to + 85 c) oscillator clock configuration parameter test condition min typ max units crystal x in c1 x out main oscillation frequency 2.7 v ? 5.5 v 0.4 ? 8 mhz 2.0 v ? 5.5 v 0.4 ? 4 ceramic oscillator x in c1 x out main oscillation frequency 2.7 v ? 5.5 v 0.4 ? 8 2.0 v ? 5.5 v 0.4 ? 4 external clock x in x out x in input frequency 2.7 v ? 5.5 v 0.4 ? 8 2.0 v ? 5.5 v 0.4 ? 4 rc oscillator x in x out r frequency 5.0 v 0.4 ? 2 mhz frequency 3.0 v 0.4 ? 1 table 16-8. sub oscillation characteristics (t a = ? 25 c to + 85 c) oscillator clock configuration parameter test condition min typ max units crystal x in c1 x out sub oscillation frequency 2.0 v ? 5.5 v 32 32.768 35 khz external clock x in x out xt in input frequency 2.0 v ? 5.5 v 32 ? 100
s3c9228/p9228 elect rical data 16- 11 table 16-9. main oscillation stabilization time (t a = ? 25 c to + 85 c, v dd = 2.0 v to 5.5 v) oscillator test condition min typ max unit crystal fx > 1 mhz ? ? 30 ms ceramic oscillation stabilization occurs when vdd is equal to the minimum oscillator voltage ranage. ? ? 10 ms external clock x in input high and low width (t xh , t xl ) 62.5 ? 1250 ns t x t xl v dd -0.1 v 0.1 v x in 1/fx figure 16-6. clock timing measurement at x in
electrical data s3c 9228/p9228 16- 12 table 16-10. sub oscillation stabilization time (t a = ? 25 c to + 85 c, v dd = 2.0 v to 5.5 v) oscillator test condition min typ max unit crystal ? ? ? 10 s external clock xt in input high and low width (t xh , t xl ) 5 ? 15 m s t xth t xtl v dd -0.1 v 0.1 v xt in 1/fxt figure 16-7. clock timing measurement at xt in
s3c9228/p9228 elect rical data 16- 13 2 mhz 6.25 khz (main)/8.2 khz(sub) 1 2 6 supply voltage (v) instruction clock = 1/4n x oscillator frequency (n = 1, 2, 8, 16) 1.0 mhz instruction clock 8 mhz 4 mhz fx (main/sub oscillation frequency) 400 khz 2.7 5.5 400 khz (main)/32.8 khz(sub) figure 16-8. operating voltage range
electrical data s3c 9228/p9228 16- 14 notes
s3c9228/p9228 mechanical data 1 7- 1 17 mechanical data overview the s3c9228/p9228 microcontroller is currently available in a 42-pin sdip and 44-pin qfp package. note : dimensions are in millimeters. 39.50 max 39.10 0 .2 0.50 0.1 1.78 (1.77) 0.51 min 3.30 0.3 3.50 0.2 5.08 max 42-sdip-600 0-15 1.00 0.1 0.25 + 0.1 - 0.05 15.24 14.00 0 .2 #42 #22 #21 #1 figure 17-1. 42-sdip-600 package dimensions
mechanical data s3c9228/p9228 1 7- 2 44-qfp-1010b #44 note : dimensions are in millimeters. 10.00 0.2 13.20 0.3 10.00 0.2 13.20 0.3 #1 0.35 + 0.10 - 0.05 0.80 (1.00) 0.10 max 0.80 0.20 0.05 min 2.05 0.10 2.30 max 0.15 + 0.10 - 0.05 0-8 figure 17-2. 44-qfp-1010b package dimensions
s3c9228/p9228 S3P9228 otp 18- 1 18 S3P9228 otp overview the S3P9228 single-chip cmos microcontroller is the otp (one time programmable) version of the s3c9228 microcontroller. it has an on-chip otp rom instead of masked rom. the eprom is accessed by serial data format. the S3P9228 is fully compatible with the s3c9228, both in function and in pin configuration. because of its simple programming requirements, the S3P9228 is ideal for use as an evaluation chip for the s3c9228. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 s3c9228 (44-qfp) p1.0/ad0/int p1.1/ad1/int sdat /p1.2/ad2/int sclk /p1.3/ad3/int v dd /v dd v ss /v ss x out x in v pp /test xt in xt out reset reset / reset p2.3 p2.2/si seg0/p2.1/so seg1/p2.0/sck seg2/p3.1/intp seg3/p3.0/intp seg4/p4.0 seg5/p4.1 seg6/p4.2 seg7/p4.3 33 32 31 30 29 28 27 26 25 24 23 com5/seg18/p5.6 com6/seg17/p5.5 com7/seg16/p5.4 seg15/p5.3 seg14/p5.2 seg13/p5.1 seg12/p5.0 seg11/p4.7 seg10/p4.6 seg9/p4.5 seg8/p4.4 44 43 42 41 40 39 38 37 36 35 34 p0.5 p0.4 p0.3/buz/int p0.2/int p0.1/t1clk/int p0.0/taout/int com0/p6.3 com1/p6.2 com2/p6.1 com3/p6.0 com4/seg19/p5.7 figure 18-1. S3P9228 44-qfp pin assignments
S3P9228 otp s3c9228/p9228 18- 2 com1/p6.2 com0/p6.3 p0.0/taout/int p0.1/t1clk/int p0.2/int p0.3/buz/int p1.0/ad0/int p1.1/ad1/int sdat /p1.2/ad2/int sclk /p1.3/ad3/int v dd /v dd v ss /v ss x out x in v pp /test xt in xt out reset reset / reset p2.3 p2.2/si seg0/p2.1/so s3c9228 (42-sdip) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 com2/p6.1 com3/p6.0 com4/seg19/p5.7 com5/seg18/p5.6 com6/seg17/p5.5 com7/seg16/p5.4 seg15/p5.3 seg14/p5.2 seg13/p5.1 seg12/p5.0 seg11/p4.7 seg10/p4.6 seg9/p4.5 seg8/p4.4 seg7/p4.3 seg6/p4.2 seg5/p4.1 seg4/p4.0 seg3/p3.0/intp seg2/p3.1/intp seg1/p2.0/sck 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 figure 18-2. S3P9228 42-sdip pin assignments
s3c9228/p9228 S3P9228 otp 18- 3 table 18-1. descriptions of pins used to read/write the eprom main chip during programming pin name pin name pin no. i/o function p1.2 sdat 3 (9) i/o serial data pin. output port when reading and input port when writing. can be assigned as a input/push-pull output port. p1.3 sclk 4 (10) i/o serial clock pin. input only pin. test v pp (test) 9 (15) i power supply pin for eprom cell writing (indicates that otp enters into the writing mode). when 12.5 v is applied, otp is in writing mode and when 5 v is applied, otp is in reading mode. (option) reset reset 12 (18) i chip initialization v dd /v ss v dd /v ss 5/6 (11/12) i logic power supply pin. v dd should be tied to + 5 v during programming. note : parentheses indicate pin number for 42-sdip package. table 18-2. comparison of S3P9228 and s3c9228 features characteristic S3P9228 s3c9228 program memory 8 kbyte eprom 8 kbyte mask rom operating voltage (v dd ) 2.0 v to 5.5 v 2.0 v to 5.5 v otp programming mode v dd = 5 v, v pp (test)=12.5v pin configuration 44-qfp, 42-sdip 44-qfp, 42-sdip eprom programmability user program 1 time programmed at the factory operating mode characteristics when 12.5 v is supplied to the v pp (test) pin of the s3p72c8, the eprom programming mode is entered. the operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in table 17-3 below. table 18-3. operating mode selection criteria v dd v pp (test) reg/mem address (a15-a0) r/w mode 5 v 5 v 0 0000h 1 eprom read 12.5 v 0 0000h 0 eprom program 12.5 v 0 0000h 1 eprom verify 12.5 v 1 0e3fh 0 eprom read protection note : "0" means low level; "1" means high level.
S3P9228 otp s3c9228/p9228 18- 4 table 18-4. d.c. electrical characteristics (t a = ? 25 c to + 85 c, v dd = 2.0 v to 5.5 v) parameter symbol conditions min typ max unit supply current (1) i dd1 run mode: v dd = 5 v 10% 8.0 mhz ? 6.0 12.0 ma crystal oscillator c1 = c2 = 22pf 4.19 mhz 3.0 6.0 v dd = 3 v 10% 8.0 mhz 2.5 5.0 4.19 mhz 1.5 3.0 i dd2 idle mode: v dd = 5 v 10% 8.0 mhz 1.3 3.0 crystal oscillator c1 = c2 = 22pf 4.19 mhz 1.0 2.0 v dd = 3 v 10% 8.0 mhz 0.8 1.6 4.19 mhz 0.4 0.8 i dd3 run mode: v dd = 3 v 10%, 32 khz crystal oscillator 15 30 m a i dd4 idle mode: v dd = 3 v 10%, 32 khz crystal oscillator 6 15 i dd5 stop mode; v dd = 5 v 10%, t a = 25 c 0.5 3 stop mode; v dd = 3 v 10%, t a = 25 c 0.3 2 notes: 1. supply current does not include current drawn through internal pull-up resistors, lcd voltage dividing resistors, and adc. 2. i dd1 and i dd2 include power consumption for subsystem clock oscillation. 3. i dd3 and i dd4 are current when main system clock oscillation stops and the subsystem clock is used. 4. i dd5 is current when main system clock and subsystem clock oscillation stops.
s3c9228/p9228 S3P9228 otp 18- 5 2 mhz 6.25 khz (main)/8.2 khz(sub) 1 2 6 supply voltage (v) instruction clock = 1/4n x oscillator frequency (n = 1, 2, 8, 16) 1.0 mhz instruction clock 8 mhz 4 mhz fx (main/sub oscillation frequency) 400 khz 2.7 5.5 400 khz (main)/32.8 khz(sub) figure 18-3. standard operating voltage range
S3P9228 otp s3c9228/p9228 18- 6 notes
s3c9228/p9228 devel opment tools 19- 1 19 development tools overview samsung provides a powerful and easy-to-use development support system in turn key form. the development support system is configured with a host system, debugging tools, and support software. for the host system, any standard computer that operates with ms-dos as its operating system can be used. one type of debugging tool including hardware and software is provided: the sophisticated and powerful in-circuit emulator, smds2+, for s3c7, s3c8, s3c9 families of microcontrollers. the smds2+ is a new and improved version of smds2. samsung also offers support software that includes debugger, assembler, and a program for setting options. shine samsung host interface for in-circuit emulator, shine, is a multi-window based debugger for smds2+. shine provides pull-down and pop-up menus, mouse support, function/hot keys, and context-sensitive hyper-linked help. it has an advanced, multiple-windowed user interface that emphasizes ease of use. each window can be sized, moved, scrolled, highlighted, added, or removed completely. sama assembler the samsung arrangeable microcontroller (sam) assembler, sama, is a universal assembler, and generates object code in standard hexadecimal format. assembled program code includes the object code that is used for rom data and required smds program control data. to assemble programs, sama requires a source file and an auxiliary definition (def) file with device specific information. sasm86 the sasm86 is an relocatable assembler for samsung's s3c9-series microcontrollers. the sasm86 takes a source file containing assembly language statements and translates into a corresponding source code, object code and comments. the sasm86 supports macros and conditional assembly. it runs on the ms-dos operating system. it produces the relocatable object code only, so the user should link object file. object files can be linked with other object files and loaded into memory. hex2rom hex2rom file generates rom code from hex file which has been produced by assembler. rom code must be needed to fabricate a microcontroller which has a mask rom. when generating the rom code (.obj file) by hex2rom, the value ?ff? is filled into the unused rom area up to the maximum rom size of the target device automatically. target boards target boards are available for all s3c9-series microcontrollers. all required target system cables and adapters are included with the device-specific target board.
development tools s3c9228/p9228 19- 2 bus smds2+ rs-232c pod probe adapter prom/otp writer unit ram break/display unit trace/timer unit sam8 base unit power supply unit ibm-pc at or compatible tb9228 target board eva chip target application system figure 19-1. smds product configuration (smds2+)
s3c9228/p9228 devel opment tools 19- 3 tb9228 target board the tb9228 target board is used for the s3c9228 microcontroller. it is supported by the smds2+ development system. tb9228 sm1347a gnd v cc to user_v cc off on smds2 smds2+ j101 42sdip j102 44qfp 1 5 15 21 10 42 40 25 22 30 35 1 5 15 22 10 44 40 30 23 35 25 20 p2 25 160 30 20 10 1 150 140 130 50 60 70 80 90 100 110 120 c14 reset r1 d1 c1 c11 u2 r7 r8 y1 c7 cb + c9 c10 j1 c3 c4 c5 c6 t1 t2 t3 t4 idle + stop + r5 r4 c20 t16 t15 t14 t13 t12 t11 t10 t9 20 10 1 51 76 26 rev.0 '2002.03.30 cn1 figure 19-2. tb9228 target board configuration
development tools s3c9228/p9228 19- 4 table 19-1. power selection settings for tb9228 "to user_v cc " settings operating mode comments to user_v cc off on target system smds2/smds2+ tb9228 v cc v ss v cc the smds2/smds2+ supplies v cc to the target board (evaluation chip) and the target system. to user_v cc off on target system smds2/smds2+ tb9228 external v cc v ss v cc the smds2/smds2+ supplies v cc only to the target board (evaluation chip). the target system must have its own power supply. note : the following symbol in the "to user_v cc " setting column indicates the electrical short (off) configuration:
s3c9228/p9228 devel opment tools 19- 5 smds2+ selection (sam8) in order to write data into program memory that is available in smds2+, the target board should be selected to be for smds2+ through a switch as follows. otherwise, the program memory writing function is not available. table 19-2. the smds2+ tool selection setting "sw1" setting operating mode smds2 smds2+ target board r/w r/w smds2+ table 19-3. using single header pins as the input path for external trigger sources target board part comments external triggers ch1 ch2 connector from external trigger sources of the application system you can connect an external trigger source to one of the two external trigger channels (ch1 or ch2) for the smds2+ breakpoint and trace functions. idle led the green led is on when the evaluation chip (s3e9220) is in idle mode. stop led the red led is on when the evaluation chip (s3e9220) is in stop mode.
development tools s3c9228/p9228 19- 6 j101 42-sdip j102 44-qfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 43 44 45 46 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 50 49 48 47 p6.2 p6.3 p0.0 p0.1 p0.2 p0.3 p1.0 p1.1 p1.2 p1.3 user_vcc vss nc nc vss nc nc demo_rstb p2.3 p2.2 p2.1 nc nc nc nc p6.1 p6.0 p5.7 p5.6 p5.5 p5.4 p5.3 p5.2 p5.1 p5.0 p4.7 p4.6 p4.5 p4.4 p4.3 p4.2 p4.1 p4.0 p3.0 p3.1 p2.0 nc nc nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 45 46 47 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 50 49 48 p1.0 p1.1 p1.2 p1.3 user_vcc vss nc nc vss nc nc demo_rstb p2.3 p2.2 p2.1 p2.0 p3.1 p3.0 p4.0 p4.1 p4.2 p4.3 nc nc nc p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 p6.3 p6.2 p6.1 p6.0 p5.7 p5.6 p5.5 p5.4 p5.3 p5.2 p5.1 p5.0 p4.7 p4.6 p4.5 p4.4 nc nc nc figure 19-3. connectors (j101, j102) for tb9228
s3c9228/p9228 devel opment tools 19- 7 target board target system target cable for connector part name: ap42sd order code: sm6538 j101 1 42 21 22 j101 1 42 21 22 50-pin dip connector figure 19-4. s3c9228 probe adapter for 42-sdip package target board target system 50-pin connector target cable for 50-pin connector part name: ap50d-a order code: sm6305 50-pin connector j102 1 44 22 23 j102 1 44 22 23 figure 19-5. s3c9228 probe adapter for 44-qfp package
development tools s3c9228/p9228 19- 8 notes
s3c9228/p9228 product overview 1- 1 1 product overview sam8 8rc ri product family samsung's sam88rcri family of 8-bit single-chi p cmos microcontrollers offer fast and efficient cpu, a wide range of integrated peripherals, and supports otp device . a dual address/data bus architecture and bit- or nibble-configurable i/o ports provide a flexible programming environment for applications with varied memory and i/o requirements. timer/counters with selectable operating modes are included t o support real-time operations. s3c9228/p9228 microcontroller the s3c9228 can be used for dedicated control functions in a variety of applications, and is especially designed for application with frs or etc. the s3c9228/p9228 single-chip 8-bit microcontroller is fabricated using an advanced cmos process. it is built around the powerful sam88rcri cpu core. stop and idle power-down modes were implemented to reduce power consumption. to increase on-chip register space, the size of the internal register file was logically expanded. the s3c9228/p9228 has 8k-byte of program rom, and 264-byte of ram (including 16-byte of working register and 20-byte lcd display ram). using the sam 88rcri design approach, the following peripherals were integrated with the sam88rcri core: ? 7 configurable i/o ports including ports shared with segment/common drive outputs ? 10-bit programmable pins for external interrupts ? one 8-bit basic timer for oscillation stabilization and watch-dog functions ? two 8-bit timer/counters with selectable operating modes ? watch timer for real time ? 4 channel a/d converter ? 8-bit serial i/o interface otp the s3c9228 microcontroller is also available in otp (one time programmable) version. S3P9228 microcontroller has an on-chip 8k-byte one-time-programmable eprom instead of masked rom. the S3P9228 is comparable to s3c9228 , both in function and in pin configuration.
product overview s3c9228/p9228 1- 2 features cpu sam88rcri cpu core memory 8192 8 bits program memory (rom) 264 8 bits data memory (ram) (including lcd data memory) instruction set 41 instructions idle and stop instructions added for power-down modes 36 i/o pins i/o: 34 pins (44-pin qfp, 42-pin sdip) output only: 2 pins (44-pin qfp) interrupts 14 interrupt source and 1 vector one interrupt level 8-bit basic timer watchdog timer function 3 kinds of clock source two 8-bit timer/counters the programmable 8-bit timer/counters external event counter function configurable as one 16-bit timer/counters watch timer interval time: 3.91ms, 0.25s, 0.5s, and 1s at 32.768 khz 0.5/1/2/4 khz selectable buzzer output clock source generation for lcd lcd controller/driver 16 segments and 8 common terminals 3, 4, and 8 common selectable internal resistor circuit for lcd bias 8-bit serial i/o interface 8-bit transmit/receive mode 8-bit receive mode lsb-first or msb-first transmission selectable internal or external clock source a/d converter 10-bit converter resolution 50us conversion speed at 1mhz f adc clock 4-channel two power-down modes idle: only cpu clock stops stop: system clock and cpu clock stop oscillation sources crystal, ceramic, or rc for main clock main clock frequency: 0.4 mhz - 8mhz 32.768 khz crystal oscillation circuit for sub clock instruction execution times 500ns at 8mhz fx(minimum) operating voltage range 2.0 v to 5.5 v at 0.4 - 4.2mhz 2.7 v to 5.5 v at 0.4 - 8mhz operating temperature range -25 c to +85 c package type 44-pin qfp, 42-pin sdip
s3c9228/p9228 product overview 1- 3 block diagram 8-bit timer/ countera port i/o and interrupt control sam88rcri cpu reset x in xt in i/o port 0 8-kbyte rom 264-byte register file x out xt out 16-bit timer/ counter1 8-bit timer/ counterb taout/ p0.0 t1clk/ p0.1 p0.0/taout/int p0.1/t1clk/int p0.2/int p0.3/buz/int p0.4 p0.5 i/o port 1 p1.0/ad0/int p1.1/ad1/int p1.2/ad2/int p1.3/ad3/int i/o port 2 p2.0/sck/seg1 p2.1/so/seg0 p2.2/si p2.3 i/o port 3 p3.0/intp/seg3 p3.1/intp/seg2 i/o port 4 p4.0-p4.7/ seg4-seg11 i/o port 5 p5.0-p5.3/ seg12-seg15 p5.4-p5.7/ seg16-seg19/ com7-com4 watchdog timer basic timer watch timer lcd driver/ controller sio a/d converter com0-com3/p6.3-p6.0 com4-com7/ seg19-seg16/p5.7-p5.4 seg0-seg1/p2.1-p2.0 seg2-seg3/p3.1-p3.0 seg4-seg11/p4.0-p4.7 p2.0/sck/seg1 p2.1/so/seg0 p2.2/si buz/p0.3 p1.0-p1.3/ad0-ad3 seg12-seg15/p5.0-p5.3 i/o port 6 p6.0-p6.3/com3-com0 figure 1-1. block diagram
product overview s3c9228/p9228 1- 4 pin assignments 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 s3c9228 (44-qfp) p1.0/ad0/int p1.1/ad1/int p1.2/ad2/int p1.3/ad3/int v dd v ss x out x in test xt in xt out reset p2.3 p2.2/si seg0/p2.1/so seg1/p2.0/sck seg2/p3.1/intp seg3/p3.0/intp seg4/p4.0 seg5/p4.1 seg6/p4.2 seg7/p4.3 33 32 31 30 29 28 27 26 25 24 23 com5/seg18/p5.6 com6/seg17/p5.5 com7/seg16/p5.4 seg15/p5.3 seg14/p5.2 seg13/p5.1 seg12/p5.0 seg11/p4.7 seg10/p4.6 seg9/p4.5 seg8/p4.4 44 43 42 41 40 39 38 37 36 35 34 p0.5 p0.4 p0.3/buz/int p0.2/int p0.1/t1clk/int p0.0/taout/int com0/p6.3 com1/p6.2 com2/p6.1 com3/p6.0 com4/seg19/p5.7 figure 1-2. s3c9228 44-qfp pin assignments
s3c9228/p9228 product overview 1- 5 com1/p6.2 com0/p6.3 p0.0/taout/int p0.1/t1clk/int p0.2/int p0.3/buz/int p1.0/ad0/int p1.1/ad1/int p1.2/ad2/int p1.3/ad3/int v dd v ss x out x in test xt in xt out reset p2.3 p2.2/si seg0/p2.1/so s3c9228 (42-sdip) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 com2/p6.1 com3/p6.0 com4/seg19/p5.7 com5/seg18/p5.6 com6/seg17/p5.5 com7/seg16/p5.4 seg15/p5.3 seg14/p5.2 seg13/p5.1 seg12/p5.0 seg11/p4.7 seg10/p4.6 seg9/p4.5 seg8/p4.4 seg7/p4.3 seg6/p4.2 seg5/p4.1 seg4/p4.0 seg3/p3.0/intp seg2/p3.1/intp seg1/p2.0/sck 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 figure 1-3. s3c9228 42-sdip pin assignments
product overview s3c9228/p9228 1- 6 pin descriptions table 1- 1 . pin descriptions pin names pin type pin description circuit number pin numbers share pins p0.0 p0.1 p0.2 p0.3 i/o 1-bit programmable i/o port. schmitt trigger input or push-pull, open-drain output and software assignable pull-ups. e-4 39(3) 40(4) 41(5) 42(6) taout/int t1clk/int int buz/int p0.4-p0.5 o 1-bit programmable output port. c 43-44 p1.0 p1.1 p1.2 p1.3 i/o 1-bit programmable i/o port. schmitt trigger input or push-pull, open-drain output and software assignable pull-ups. f-16a 1(7) 2(8) 3(9) 4(10) ad0/int ad1/int ad2/int ad3/int p2.0 p2.1 i/o 1-bit programmable i/o port. schmitt trigger input or push-pull, open-drain h-32a 16(22) 15(21) sck/seg1 so/seg0 p2.2 p2.3 i/o output and software assignable pull-ups. e-4 14(20) 13(19) si ? p3.0 p3.1 i/o 1-bit programmable i/o port. schmitt trigger input or push-pull, open-drain output and software assignable pull-ups. h-32b 18(24) 17(23) intp/seg3 intp/seg2 p4.0?p4.7 i/o 1-bit programmable i/o port. input or push-pull, open-drain output and software assignable pull-ups. h-32 19-26(25-32) seg4-seg11 p5.0?p5.3 i/o 1-bit programmable i/o port. input or push-pull, open-drain output and h-32 27-30(33-36) seg12-seg15 p5.4?p5.7 software assignable pull-ups. 31-34(37-40) seg16-seg19 /com7-com4 p6.0-p6.3 i/o 1-bit programmable i/o port. input or push-pull, open-drain output and software assignable pull-ups. h-32 35-38 (41-42,1-2) com3-com0 note: parentheses indicate pin number for 42-sdip-600 package.
s3c9228/p9228 product overview 1- 7 table 1- 1 . pin descriptions (continued) pin names pin type pin description circuit number pin numbers share pins v dd , v ss ? power input pins for internal power block ? 5,6(11,12) ? x out , x in ? main oscillator pins for main clock ? 7,8(13,14) xt out , xt in ? sub oscillator pins for sub clock ? 11,10(17,16) ? test ? chip test input pin hold gnd when the device is operating ? 9(15) ? reset i reset signal input pin. schmitt trigger input with internal pull-up resistor. b 12(18) ? int i/o external interrupts input. e-4 f-16a 39-42(3-6) 1-4(7-10) p0.0-p0.3 p1.0-p1.3 intp i/o key scan interrupts inputs. h-32b 17-18(23-24) p3.1-p3.0 t1clk i/o timer 1/a external clock input. e-4 40(4) p0.1 taout i/o timer 1/a clock output. e-4 39(3) p0.0 ad0-ad3 i/o analog input pins for a/d converts module. f-16a 1-4(7-10) p1.0-p1.3 buz i/o buzzer signal output. e-4 42(6) p0.3 sck so i/o serial clock, serial data output, serial data input h-32a 16-15(22-21) p2.0-p2.1 si e-4 14(20) p2.2 seg0-seg1 i/o lcd segment signal output h-32a 15-16(21-22) p2.1-p2.0 seg2-seg3 h-32b 17-18(23-24) p3.1-p3.0 seg4-seg19 h-32 19-34(25-40) p4.0-p4.7 p5.0-p5.7 com0-com7 i/o lcd common signal output h-32 38-31 (2-1,42-37) p6.3-p6.0 p5.7-p5.4 note: parentheses indicate pin number for 42-sdip-600 package.
product overview s3c9228/p9228 1- 8 pin circuit diagrams reset v dd pull-up resistor noise filter figure 1-4. pin circuit type b v dd output output disable data v ss figure 1-5. pin circuit type c
s3c9228/p9228 product overview 1- 9 v dd pull-up enable v dd i/o pull-up resistor output disable data external interrupt input open-drain figure 1-7. pin circuit type e-4 v dd i/o pull-up resistor circuit type e to adc data aden adselect open-drain en data output disable pull-up enable figure 1-8. pin circuit type f-16a
product overview s3c9228/p9228 1- 10 out seg/com v lc3 output disable v lc2 v lc1 v ss v lc4 v lc5 figure 1-9. pin circuit type h-23
s3c9228/p9228 product overview 1- 11 v dd pull-up enable v dd i/o pull-up resistor data open-drain en circuit type h-23 lcd out en com/seg output disable figure 1-10. pin circuit type h-32 v dd pull-up enable v dd i/o pull-up resistor data open-drain en circuit type h-23 lcd out en com/seg output disable figure 1-11. pin circuit type h-32a
product overview s3c9228/p9228 1- 12 v dd pull-up enable v dd i/o pull-up resistor data open-drain en circuit type h-23 lcd out en com/seg output disable port enable (lmod.5) figure 1-12. pin circuit type h-32b
s3c9228/p9228 address spaces 2- 1 2 address spaces overview the s3c9228/p9228 microcontroller has three kinds of address space: ? program memory (rom) ? internal register file ? lcd display register file a 16 -bit address bus supports program memory operations. special instructions and related internal logic determine when the 1 6 -bit bus carries addresses for program memory. a separate 8 -bit register bus carries addresses and data between the cpu and the internal register file. the s3c9228 has 8k bytes of mask-programmable program memory on-chip . the s3c9228/p9228 microcontroller has 244 bytes general-purpose registers in its internal register file and the 20 bytes for lcd display memory is implemented in the internal register file too. fifty-six bytes in the register file are mapped for system and peripheral control functions.
address spaces s3c9228/p9228 2- 2 program memory (rom) program memory (rom) stores program code or table data. the s3c9228 has 8k bytes of mask- programable program memory. the program memory address range is therefore 0h-1fffh. the first 2 bytes of the rom (0000h? 0001h) are an interrupt vector address. the program reset address in the rom is 0100h. 8,192 256 1fffh 0100h 0 8k bytes internal program memory area interrupt vector 1 2 0002h 0001h program start 0000h (decimal) (hex) figure 2- 1. s3c9228/p9228 program memory address space
s3c9228/p9228 address spaces 2- 3 register architecture the upper 72 bytes of the s3c9228/p9228 's internal register file are addressed as working registers, system cont r ol registe r s and periphe r al control registers. the lower 184 bytes of internal register file (00h? b7 h) is called the general purpose register space . for many sam88rcri microcontrollers, the addressable area of the internal register file is further expanded by the additional of one or more register pages at general purpose register space (00h?bfh). this register file expansion is implemented by page 1 in the s3c9228/p9228 . the page 1 ( 20 8 b its ) is for lcd display register and can be used as general-purpose registers. ffh b8h ~ b7h 00h 184 bytes 72 bytes of common area d0h cfh e0h dfh working registers system control registers peripheral control registers general purpose register file and stack area (page 0) 3fh 00h lcd display registers (page 1) peripheral control registers c0h bfh general purpose register file 13h 64 bytes figure 2- 2 . internal register file organization
address spaces s3c9228/p9228 2- 4 common working register area (c0h?cfh) the sam88rcr i register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time. this16-byte address range is called common area. that is, locations in this area can be used as working registers by operations that address any location on any page in the register file. typically, these working registers serve as temporary buffers for data operations between different pages. the register (r) addressing mode can be used to access this area registers are addressed either as a single 8-bit register or as a paired 16-bit register. in 16-bit register pairs, the address of the first 8-bit register is always an even number and the address of the next register is an odd number. the most significant byte of the 16-bit data is always stored in the even-numbered register; the least significant byte is always stored in the next (+ 1) odd-numbered register. msb rn lsb rn + 1 n = even address figure 2- 3 . 16-bit register pairs + + programming tip ? addressing the common working register area as the following examples show, you should access working registers in the common area, locations c0h?cfh, using working register addressing mode only. example s: 1. ld 0c2h,40h ; invalid addressing mode! use working register addressing instead: ld r2,40h ; r2 (c2h) ? the value in location 40h 2. add 0c3h,#45h ; invalid addressing mode! use working register addressing instead: add r3,#45h ; r3 (c3h) ? r3 + 45h
s3c9228/p9228 address spaces 2- 5 system stack s 3c9 -series microcontrollers use the system stack for subroutine calls and returns and to store data. the push and pop instructions are used to control system stack operations. the s3c9228/p9228 architecture supports stack operations in the internal register file. stack operations return addresses for procedure calls and interrupts and data are stored on the stack. the contents of the pc are saved to stack by a call instruction and restored by the ret instruction. when an interrupt occurs, the contents of the pc and the flags register are pushed to the stack. the iret instruction then pops these values back to their original locations. the stack address is always decremented before a push operation and incremented after a pop operation. the stack pointer (sp) always points to the stack frame stored on the top of the stack, as shown in figure 2-4 . stack contents after a call instruction stack contents after an interrupt top of stack flags pch pcl pcl pch top of stack low address high address figure 2- 4 . stack operations stack pointer (sp) register location d9h contains the 8-bit stack pointer (sp) that is used for system stack operations. after a reset, the sp value is undetermined. because only internal memory space is implemented in the s3c9228/p9228 , the sp must be initialized to an 8- bit value in the range 00h? b7 h. note in case a stack pointer is initialized to 00h, it is decrea s ed to ffh when stack operation starts. this means that a stack pointer access invalid stack area.
address spaces s3c9228/p9228 2- 6 + + programming tip ? standard stack operations using push and pop the following example shows you how to perform stack operations in the internal register file using push and pop instructions: ld sp,#0 b8 h ; sp ? b8 h (normally, the sp is set to 0 b8 h by the ; initialization routine) ? ? ? push sym ; stack address 0b 7 h ? sym push wt con ; stack address 0b 6 h ? wt con push 20h ; stac k address 0b 5 h ? 20h push r3 ; stack address 0b 4 h ? r3 ? ? ? pop r3 ; r3 ? stack address 0b 4 h pop 20h ; 20h ? stack address 0b 5 h pop wt con ; wt con ? stack address 0b 6 h pop sym ; sym ? stack address 0b 7 h
s3c9228/p9228 addressing modes 3- 1 3 addressing modes overview instructions that are stored in program memory are fetched for execution using the program counter. instructions indicate the operation to be performed and the data to be operated on. addressing mode is the method used to determine the location of the data operand. the operands specified in sam88rc r i instructions may be condition codes, immediate data, or a location in the register file, program memory, or data memory. the sam88rcri instruction set supports six explicit addressing modes. not all of these addressing modes are available for each instruction. the addressing modes and their symbols are as follows: ? register (r) ? indirect register (ir) ? indexed (x) ? direct addr ess (da) ? relative address (ra) ? immediate (im)
addressing modes s3c9228/p9228 3- 2 register addressing mode (r) in register addressing mode, the operand is the content of a specified register (see figure 3- 1). working register addressing differs from register a ddressing because it uses a 16- byte working register s pace in the register file and a 4-bit register within that space (see figure 3- 2). dst value used in instruction execution opcode operand 8-bit register file address point to one rigister in register file one-operand instruction (example) sample instruction: dec cntr ; where cntr is the label of an 8-bit register address program memory register file figure 3- 1 . register addressing dst opcode 4-bit working register point to the woking register (1 of 16) two-operand instruction (example) sample instruction: add r1, r2 ; where r1 = c1h and r2 = c2h program memory register file src 4 lsbs operand cfh c0h . . . . figure 3- 2 . working register addressing
s3c9228/p9228 addressing modes 3- 3 indirect register addressing mode (ir) in indirect register (ir) addressing mode, the content of the specified register or register pair is the address of the operand. depending on the instruction used, the actual address may point to a register in the register file, to program memory (rom), or to an external memory space (see figures 3- 3 through 3- 6). you can use any 8-bit register to indirectly address another register. any 16-bit register pair can be used to indirectly address another memory location. 8-bit register file address one-operand instruction (example) dst address of operand used by instruction opcode address point to one rigister in register file sample instruction: rl @shift ; where shift is the label of an 8-bit register address program memory register file value used in instruction execution operand figure 3- 3 . indirect register addressing to register file
addressing modes s3c9228/p9228 3- 4 indirect register addressing mode ( c ontinued ) dst opcode pair points to rigister pair example instruction references program memory sample instructions: call @rr2 jp @rr2 program memory register file value used in instruction operand register program memory 16-bit address points to program memory figure 3- 4 . indirect register addressing to program memory
s3c9228/p9228 addressing modes 3- 5 indirect register addressing mode (c ontinued ) dst opcode operand 4-bit working register address point to the woking register (1 of 16) sample instruction: or r6, @r2 program memory register file src 4 lsbs value used in instruction operand cfh c0h . . . . figure 3- 5 . indirect working register addressing to register file
addressing modes s3c9228/p9228 3- 6 indirect register addressing mode (c oncluded ) dst opcode 4-bit working register address sample instructions: lcd r5,@rr6 ; program memory access lde r3,@rr14 ; external data memory access lde @rr4, r8 ; external data memory access program memory register file src value used in instruction operand example instruction references either program memory or data memory program memory or data memory next 3 bits point to working register pair (1 of 8) lsb selects register pair 16-bit address points to program memory or data memory cfh . . . . c0h figure 3- 6 . indirect working register addressing to program or data memory
s3c9228/p9228 addressing modes 3- 7 indexed addressing mode (x) indexed (x) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see figure 3- 7). you can use indexed addressing mode to access locations in the internal register file or in external memory. in short offset indexed addressing mode, the 8- bit displacement is treated as a signed integer in the range of ?128 to +127. this applies to external memory accesses only (see figure 3- 8). for register file addressing, an 8-b it base address provided by the instruction is added to an 8-bit offset contained in a working register. for external memory accesses, the base address is stored in the working register pair designated in the instruction. the 8-bit or 16-bit offset given in the instruction is then added to the base address (see figure 3- 9). the only instruction that supports indexed addressing mode for the internal register file is the load instruction (ld). the ldc and lde instructions support indexed addressing mode for internal program memory, external program memory, and for external data memory, when implemented. dst opcode two-operand instruction example point to one of the woking register (1 of 16) sample instruction: ld r0, #base[r1] ; where base is an 8-bit immediate value program memory register file 4 lsbs value used in instruction operand index base address ~ ~ ~ ~ + src figure 3- 7 . indexed addressing to register file
addressing modes s3c9228/p9228 3- 8 indexed addressing mode (c ontinued ) point to working register pair (1 of 8) lsb selects 16-bit address added to offset dst opcode program memory xs (offset) 4-bit working register address sample instructions: ldc r4, #04h[rr2] ; the values in the program address (rr2 + #04h) are loaded into register r4. lde r4,#04h[rr2] ; identical operation to ldc example, except that external program memory is accessed. next 3 bits register pair src 8-bits 16-bits + program memory or data memory operand value used in instruction 16-bits register file figure 3- 8 . indexed addressing to program or data memory with short offset
s3c9228/p9228 addressing modes 3- 9 indexed addressing mode (c oncluded ) point to working register pair (1 of 8) lsb selects 16-bit address added to offset program memory 4-bit working register address sample instructions: ldc r4, #1000h[rr2] ; the values in the program address (rr2 + #1000h) are loaded into register r4. lde r4, #1000h[rr2] ; identical operation to ldc example, except that external program memory is accessed. next 3 bits register pair 8-bits 16-bits + program memory or data memory operand value used in instruction 16-bits register file opcode xl h (offset) xl l (offset) dst src figure 3- 9 . indexed addressing to program or data memory with long offset
addressing modes s3c9228/p9228 3- 10 direct address mode (da) in direct address (da) mode, the instruction provides the operand's 16-bit memory address. jump (jp) and call (call) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the pc whenever a jp or call instruction is executed. the ldc and lde instructions can use direct address mode to specify the source or destination address for load operations to program memory (ldc) or to external data memory (lde), if implemented. sample instructions: ldc r5,1234h ; the values in the program address (1234h) are loaded into register r5. lde r5,1234h ; identical operation to ldc example, except that external program memory is accessed. dst/src opcode program memory "0" or "1" lower address byte lsb selects program memory or data memory: "0" = program memory "1" = data memory memory address used upper address byte program or data memory figure 3- 10 . direct addressing for load instructions
s3c9228/p9228 addressing modes 3- 11 direct address mode (c ontinued ) opcode program memory upper address byte program memory address used lower address byte sample instructions: jp c,job1 ; where job1 is a 16-bit immediate address call display ; where display is a 16-bit immediate address next opcode figure 3- 11 . direct addressing for call and jump instructions
addressing modes s3c9228/p9228 3- 12 relative address mode (ra) in relative address (ra) mode, a two's-complement signed displacement between ? 128 and + 127 is specified in the instruction. the displacement value is then added to the current pc value. the result is the address of the next instruction to be executed. before this addition occurs, the pc contains the address of the instruction immediately following the current instruction. the instructions that support ra addressing is jr. opcode program memory displacement program memory address used sample instructions: jr ult,$ + offset ; where offset is a value in the range + 127 to - 128 next opcode + signed displacement value current instruction current pc value figure 3- 12 . relative addressing immediate mode (im) in immediate (im) addressing mode, the operand value used in the instruction is the value supplied in the operand field itself. immediate addressing mode is useful for loading constant values into registers. (the operand value is in the instruction) opcode sample instruction: ld r0,#0aah program memory operand figure 3- 13 . immediate addressing
s3c9228/p9228 control registers 4- 1 4 control registers overview in this section, detailed descriptions of the s3c9228/p9228 control registers are presented in an easy-to-read format. these descriptions will help familiarize you with the mapped locations in the register file. you can also use them as a quick-reference source when writing application programs. system and peripheral registers are summarized in table 4- 1. figure 4- 1 illustrates the important features of the standard register description format. control register descriptions are arranged in alphabetical order according to register mnemonic. more information about control registers is presented in the context of the various peripheral hardware descriptions in part ii of this manual.
control registers s3c9228/p9228 4- 2 table 4-1. sys tem and peripheral c ontrol registers (page 0) register name mnemonic address (page 0) r/w decimal hex port 0 control register p0con 235 ebh r/w port 0 pull-up resistor enable register p0pur 236 ech r/w port 0 interrupt control register p0int 237 edh r/w port 0 interrupt edge selection register p0edge 238 eeh r/w port 1 control register p1con 239 efh r/w port 1 pull-up resistor enable register p1pur 240 f0h r/w port 1 interrupt control register p1int 241 f1h r/w port 1 interrupt edge selection register p1edge 242 f2h r/w port 2 control register p2con 243 f3h r/w port 2 pull-up resistor enable register p2pur 244 f4h r/w port 3 control register p3con 245 f5h r/w port 3 pull-up resistor enable register p3pur 246 f6h r/w port 3 interrupt control register p3int 247 f7h r/w port 3 interrupt edge selection register p3edge 248 f8h r/w port 4 control register (high byte) p4conh 249 f9h r/w port 4 control register (low byte) p4conl 250 fah r/w port 5 control register (high byte) p5conh 251 fbh r/w port 5 control register (low byte) p5conl 252 fch r/w port 6 control register p6con 253 fdh r/w lcd mode register lmod 254 feh r/w location ffh is not mapped.
s3c9228/p9228 control registers 4- 3 table 4- 1. sys tem and peripheral c ontrol registers (page 0) register name mnemonic address (page 0) r/w decimal hex locations d8h-b9h are not mapped. timer b control register tbcon 202 bah r/w timer 1/a control register tacon 203 bbh r/w timer b data register tbdata 204 bch r/w timer a data register tadata 205 bdh r/w timer b counter tbcnt 206 beh r timer a counter tacnt 207 bfh r a/d converter control register adcon 208 d0h r/w a/d converter data register (high byte) addatah 209 d1h r/w a/d converter data register (low byte) addatal 210 d2h r/w oscillator control register osccon 211 d3h r/w system clock control register clkcon 212 d4h r/w system flags register flags 213 d5h r/w interrupt pending register 1 intpnd1 214 d6h r/w interrupt pending register 2 intpnd2 215 d7h r/w lcd port control register lpot 216 d8h r/w stack pointer sp 217 d9h r/w watch timer control register wtcon 218 dah r/w location dbh is not mapped. basic timer control register btcon 220 dch r/w basic timer counter btcnt 221 ddh r location deh is not mapped. system mode register sym 223 dfh r/w stop control register stpcon 224 e0h r/w sio control register siocon 225 e1h r/w sio data register siodata 226 e2h r/w sio prescaler register siops 227 e3h r/w port 0 data register p0 228 e4h r/w port 1 data register p1 229 e5h r/w port 2 data register p2 230 e6h r/w port 3 data register p3 231 e7h r/w port 4 data register p4 232 e8h r/w port 5 data register p5 233 e9h r/w port 6 data register p6 234 eah r/w
control registers s3c9228/p9228 4- 4 flags - system flags register .7 .6 .5 bit identifier reset reset value read/write r = read-only w = write-only r/w = read/write ' - ' = not used bit number: msb = bit 7 lsb = bit 0 addressing mode or modes you can use to modify register values description of the effect of specific bit settings reset value notation: '-' = not used 'x' = undetermind value '0' = logic zero '1' = logic one bit number(s) that is/are appended to the register name for bit addressing d5h register address (hexadecimal) full register name register mnemonic name of individual bit or bit function .7 .6 .5 .4 .2 .3 .1 .0 x r/w x r/w x r/w x r/w 0 r/w x r/w 0 r/w x r/w carry flag (c) 0 operation dose not generate a carry or borrow condition 1 operation generates carry-out or borrow into high-order bit7 zero flag 0 operation result is a non-zero value 1 operation result is zero sign flag 0 operation generates positive number (msb = "0") 1 operation generates negative number (msb = "1") figure 4-1. register description format
s3c9228/p9228 control registers 4- 5 ad c on ? a/d converter co ntrol register d 0 h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? 0 0 0 0 0 0 read/write ? ? r/w r/w r r/w r/w r/w .7-.6 not used for the s3c9228/p9228 .5- . 4 a/d input pin selection bits 0 0 ad0 (p1.0) 0 1 ad1 (p1.1) 1 0 ad2 (p1.2) 1 1 ad3 (p1.3) .3 end of conversion bit (read-only) 0 conversion not complete 1 conversion complete .2-.1 clock source selection bits 0 0 fxx/16 0 1 fxx/8 1 0 fxx/4 1 1 fxx .0 start or enable bit 0 disable operation 1 start operation (automatically disable operation after conversion complete)
control registers s3c9228/p9228 4- 6 btc on ? basic timer co ntrol register dch bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7- .4 watchdog timer en able bits 1 0 1 0 disable watchdog function any other value enable watchdog function .3- .2 basic timer input clock selection bits 0 0 f xx /4096 0 1 f xx /1024 1 0 f xx /128 1 1 fxx/16 .1 basic timer counter clear bit ( 1) 0 no effect 1 clear the basic timer counter value (btcnt) .0 clock frequency divider clear bit for basic timer and timer/counters (2) 0 no effect 1 clear clock frequency dividers note s 1. when "1" is written to btcon. 1 , the basic timer counter value is cleared to "00h" . immediately following the write operation, the btcon.1 value is automatically cleared to "0". 2. when "1" is written to btcon. 0 , the corresponding frequency divider is cleared to "00h". immediately following the write operation, the btcon.0 value is automatically cleared to "0".
s3c9228/p9228 control registers 4- 7 clkcon ? system clock control register d4h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 oscillator irq wake-up function bit 0 enable irq for main or sub oscillator wake-up in power down mode 1 disable irq for main or sub oscillator wake-up in power down mode . 6-.5 bits 6-5 0 always logic zero .4- .3 cpu clock (system clock) selection bits 0 0 divide by 16 ( fxx /16) 0 1 divide by 8 ( fxx /8) 1 0 divide by 2 ( fxx /2) 1 1 non-divided clock ( fxx ) . 2-.0 bits 2-0 0 always logic zero
control registers s3c9228/p9228 4- 8 flags ? system flags register d5h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value x x x x ? ? ? ? read/write r/w r/w r/w r/w ? ? ? ? .7 carry flag (c) 0 operation does not generate a carry or borrow condition .6 zero flag (z) 0 operation result is a non-zero value 1 operation result is zero .5 sign flag (s) 0 operation generates a positive number (msb = "0") 1 operation generates a negative number (msb = "1") .4 overflow flag (v) 0 operation result is +127 or 3 ?128 1 operation result is 3 +127 or ?128 .3 -.0 not used for s3c9228/p9228
s3c9228/p9228 control registers 4- 9 intpnd1 ? interrupt pending register 1 d6 h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 p1.3's interrupt pending bit 0 no interrupt pending (when read), clear pending bit (when write) 1 interrupt is pending (when read) .6 p1.2's interrupt pending bit 0 no interrupt pending (when read), clear pending bit (when write) 1 interrupt is pending (when read) . 5 p1.1's interrupt pending bit 0 no interrupt pending (when read), clear pending bit (when write) 1 interrupt is pending (when read) . 4 p1.0's interrupt pending bit 0 no interrupt pending (when read), clear pending bit (when write) 1 interrupt is pending (when read) .3 p0.3's interrupt pending bit 0 no interrupt pending (when read), clear pending bit (when write) 1 interrupt is pending (when read) . 2 p0.2's interrupt pending bit 0 no interrupt pending (when read), clear pending bit (when write) 1 interrupt is pending (when read) . 1 p0.1's interrupt pending bit 0 no interrupt pending (when read), clear pending bit (when write) 1 interrupt is pending (when read) . 0 p0.0's interrupt pending bit 0 no interrupt pending (when read), clear pending bit (when write) 1 interrupt is pending (when read) note: refer to page 5-6 to clear any pending bits.
control registers s3c9228/p9228 4- 10 intpnd2 ? interrupt pending register 2 d7 h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? 0 0 0 0 0 0 read/write ? ? r/w r/w r/w r/w r/w r/w .7 -.6 not used for s3c9228/p9228 . 5 p3.1 (intp) interrupt pending bit 0 no interrupt pending (when read), clear pending bit (when write) 1 interrupt is pending (when read) . 4 p3.0 (intp) interrupt pending bit 0 no interrupt pending (when read), clear pending bit (when write) 1 interrupt is pending (when read) .3 watch timer interrupt pending bit 0 no interrupt pending (when read), clear pending bit (when write) 1 interrupt is pending (when read) . 2 sio interrupt pending bit 0 no interrupt pending (when read), clear pending bit (when write) 1 interrupt is pending (when read) . 1 timer b interrupt pending bit 0 no interrupt pending (when read), clear pending bit (when write) 1 interrupt is pending (when read) . 0 timer 1/a interrupt pending bit 0 no interrupt pending (when read), clear pending bit (when write) 1 interrupt is pending (when read) note: refer to page 5-6 to clear any pending bits.
s3c9228/p9228 control registers 4- 11 lmod ? lcd mode control register fe h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? 0 0 0 0 0 0 0 read/write ? r/w r/w r/w r/w r/w r/w r/w .7 not used for s3c9228/p9228 .6 com pins high impedance control bit 0 normal coms signal output 1 com pins are at high impedance .5 port3 high impedance control bit 0 normal i/o 1 high impedance input .4 lcd display control bit 0 display off (cut off the lcd voltage dividing resistors) 1 normal display on .3-.2 lcd duty and bias selection bits 0 0 1/3 duty, 1/3 bias; com0?com2/seg0?seg19 0 1 1/4 duty, 1/3 bias; com0?com3/seg0?seg19 1 0 1/8 duty, 1/4 bias; com0?com7/seg0?seg15 1 1 1/8 duty, 1/5 bias; com0?com7/seg0?seg15 .1-.0 lcd clock selection bits 0 0 fw/2 7 (256 hz when fw is 32.768 khz) 0 1 fw/2 6 (512 hz when fw is 32.768 khz) 1 0 fw/2 5 (1,024 hz when fw is 32.768 khz) 1 1 fw/2 4 (2,048 hz when fw is 32.768 khz)
control registers s3c9228/p9228 4- 12 lpot ? lcd port control register d8 h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? 0 0 0 0 0 0 0 read/write ? r/w r/w r/w r/w r/w r/w r/w .7 not used for s3c9228/p9228 .6-.4 seg4-seg19 and com0-com3 selection bit seg4-7 seg8-11 seg12-15 seg16-19/ com7-com4 com0-3 p4.0-p4.3 p4.4-p4.7 p5.0-p5.3 p5.4-p5.7 p6.0-p6.3 0 0 0 seg seg seg seg/com com 0 0 1 port seg seg seg/com com 0 1 0 port port seg seg/com com 0 1 1 port port port seg/com com 1 0 0 port port port port com 1 0 1 port port port port port .3 seg3/p3.0 selection bit 0 seg port 1 normal i/o port .2 seg2/p3.1 selection bit 0 seg port 1 normal i/o port .1 seg1/p2.0 selection bit 0 seg port 1 normal i/o port .0 seg0/p2.1 selection bit 0 seg port 1 normal i/o port note: seg16-seg19 are shared with com4-com7.
s3c9228/p9228 control registers 4- 13 osccon ? oscillator control register d3 h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? ? ? 0 0 ? 0 read/write ? ? ? ? r/w r/w ? r/w .7 -.4 not used for s3c9228/p9228 .3 main oscillator control bit 0 main oscillator run 1 main oscillator stop .2 sub oscillator control bit 0 sub oscillator run 1 sub oscillator stop .1 not used for s3c9228/p9228 .0 system clock selection bit 0 select main oscillator for system clock 1 select sub oscillator for system clock
control registers s3c9228/p9228 4- 14 p0con ? port 0 control register ebh bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7-.6 p0.3/buz/int configuration bits 0 0 schmitt trigger input 0 1 push-pull output 1 0 n-channel open-drain output 1 1 alternative function (buz output) .5-.4 p0.2/int configuration bits 0 0 schmitt trigger input 0 1 push-pull output 1 0 n-channel open-drain output 1 1 not available .3-.2 p0.1/t1clk/int configuration bits 0 0 schmitt trigger input (t1clk input) 0 1 push-pull output 1 0 n-channel open-drain output 1 1 not available .1-.0 p0.0/taout/int configuration bits 0 0 schmitt trigger input 0 1 push-pull output 1 0 n-channel open-drain output 1 1 alternative function (taout output)
s3c9228/p9228 control registers 4- 15 p0int ?port 0 interrupt enable register edh bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? ? ? 0 0 0 0 read/write ? ? ? ? r/w r/w r/w r/w .7-.4 not used for s3c9228/p9228 .3 p0.3's interrupt enable bit 0 disable interrupt 1 enable interrupt .2 p0.2's interrupt enable bit 0 disable interrupt 1 enable interrupt .1 p0.1's interrupt enable bit 0 disable interrupt 1 enable interrupt .0 p0.0's interrupt enable bit 0 disable interrupt 1 enable interrupt
control registers s3c9228/p9228 4- 16 p0pur ?port 0 pull-up resistors enable register ech bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? ? ? 0 0 0 0 read/write ? ? ? ? r/w r/w r/w r/w .7-.4 not used for s3c9228/p9228 .3 p0.3's pull-up resistor enable bit 0 disable pull-up resistor 1 enable pull-up resistor .2 p0.2's pull-up resistor enable bit 0 disable pull-up resistor 1 enable pull-up resistor .1 p0.1's pull-up resistor enable bit 0 disable pull-up resistor 1 enable pull-up resistor .0 p0.0's pull-up resistor enable bit 0 disable pull-up resistor 1 enable pull-up resistor
s3c9228/p9228 control registers 4- 17 p0edge ?port 0 interrupt edge selection register eeh bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? ? ? 0 0 0 0 read/write ? ? ? ? r/w r/w r/w r/w .7-.4 not used for s3c9228/p9228 .3 p0.3's interrupt edge setting bit 0 falling edge interrupt 1 rising edge interrupt .2 p0.2's interrupt state setting bit 0 falling edge interrupt 1 rising edge interrupt .1 p0.1's interrupt state setting bit 0 falling edge interrupt 1 rising edge interrupt .0 p0.0's interrupt state setting bit 0 falling edge interrupt 1 rising edge interrupt
control registers s3c9228/p9228 4- 18 p1con ? port 1 control register efh bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7-.6 p1.3/ad3/int configuration bits 0 0 schmitt trigger input 0 1 push-pull output 1 0 n-channel open-drain output 1 1 alternative function (adc mode) .5-.4 p1.2/ad2/int configuration bits 0 0 schmitt trigger input 0 1 push-pull output 1 0 n-channel open-drain output 1 1 alternative function (adc mode) .3-.2 p1.1/ad1/int configuration bits 0 0 schmitt trigger input 0 1 push-pull output 1 0 n-channel open-drain output 1 1 alternative function (adc mode) .1-.0 p1.0/ad0/int configuration bits 0 0 schmitt trigger input 0 1 push-pull output 1 0 n-channel open-drain output 1 1 alternative function (adc mode)
s3c9228/p9228 control registers 4- 19 p1int ?port 1 interrupt enable register f1h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? ? ? 0 0 0 0 read/write ? ? ? ? r/w r/w r/w r/w .7-.4 not used for s3c9228/p9228 .3 p1.3's interrupt enable bit 0 disable interrupt 1 enable interrupt .2 p1.2's interrupt enable bit 0 disable interrupt 1 enable interrupt .1 p1.1's interrupt enable bit 0 disable interrupt 1 enable interrupt .0 p1.0's interrupt enable bit 0 disable interrupt 1 enable interrupt
control registers s3c9228/p9228 4- 20 p1pur ?port 1 pull-up resistors enable register f0h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? ? ? 0 0 0 0 read/write ? ? ? ? r/w r/w r/w r/w .7-.4 not used for s3c9228/p9228 .3 p1.3's pull-up resistor enable bit 0 disable pull-up resistor 1 enable pull-up resistor .2 p1.2's pull-up resistor enable bit 0 disable pull-up resistor 1 enable pull-up resistor .1 p1.1's pull-up resistor enable bit 0 disable pull-up resistor 1 enable pull-up resistor .0 p1.0's pull-up resistor enable bit 0 disable pull-up resistor 1 enable pull-up resistor
s3c9228/p9228 control registers 4- 21 p1edge ?port 1 interrupt edge selection register f2h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? ? ? 0 0 0 0 read/write ? ? ? ? r/w r/w r/w r/w .7-.4 not used for s3c9228/p9228 .3 p1.3's interrupt edge setting bit 0 falling edge interrupt 1 rising edge interrupt .2 p1.2's interrupt state setting bit 0 falling edge interrupt 1 rising edge interrupt .1 p1.1's interrupt state setting bit 0 falling edge interrupt 1 rising edge interrupt .0 p1.0's interrupt state setting bit 0 falling edge interrupt 1 rising edge interrupt
control registers s3c9228/p9228 4- 22 p2con ? port 2 control register f3h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7-.6 p2.3 configuration bits 0 0 schmitt trigger input 0 1 push-pull output 1 0 n-channel open-drain output 1 1 not available .5-.4 p2.2/si configuration bits 0 0 schmitt trigger input (si) 0 1 push-pull output 1 0 n-channel open-drain output 1 1 not available .3-.2 p2.1/so configuration bits 0 0 schmitt trigger input 0 1 push-pull output 1 0 n-channel open-drain output 1 1 alternative function (so out) .1-.0 p2.0/sck configuration bits 0 0 schmitt trigger input (sck in) 0 1 push-pull output 1 0 n-channel open-drain output 1 1 alternative function (sck out)
s3c9228/p9228 control registers 4- 23 p2pur ?port 2 pull-up resistors enable register f4h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? ? ? 0 0 0 0 read/write ? ? ? ? r/w r/w r/w r/w .7-.4 not used for s3c9228/p9228 .3 p2.3's pull-up resistor enable bit 0 disable pull-up resistor 1 enable pull-up resistor .2 p2.2's pull-up resistor enable bit 0 disable pull-up resistor 1 enable pull-up resistor .1 p2.1's pull-up resistor enable bit 0 disable pull-up resistor 1 enable pull-up resistor .0 p2.0's pull-up resistor enable bit 0 disable pull-up resistor 1 enable pull-up resistor
control registers s3c9228/p9228 4- 24 p3con ? port 3 control register f5h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? ? ? 0 0 0 0 read/write ? ? ? ? r/w r/w r/w r/w .7-.4 not used for s3c9228/p9228 .3-.2 p3.1/seg2/intp configuration bits 0 0 schmitt trigger input 0 1 push-pull output 1 0 n-channel open-drain output 1 1 not available .1-.0 p3.0/seg3/intp configuration bits 0 0 schmitt trigger input 0 1 push-pull output 1 0 n-channel open-drain output 1 1 not available
s3c9228/p9228 control registers 4- 25 p3int ?port 3 interrupt enable register f7h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? ? ? ? ? 0 0 read/write ? ? ? ? ? ? r/w r/w .7-.2 not used for s3c9228/p9228 .1 p3.1's interrupt enable bit 0 disable interrupt 1 enable interrupt .0 p3.0's interrupt enable bit 0 disable interrupt 1 enable interrupt
control registers s3c9228/p9228 4- 26 p3pur ?port 3 pull-up resistors enable register f6h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? ? ? ? ? 0 0 read/write ? ? ? ? ? ? r/w r/w .7-.2 not used for s3c9228/p9228 .1 p3.1's pull-up resistor enable bit 0 disable pull-up resistor 1 enable pull-up resistor .0 p3.0's pull-up resistor enable bit 0 disable pull-up resistor 1 enable pull-up resistor
s3c9228/p9228 control registers 4- 27 p3edge ?port 3 interrupt edge selection register f8h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? ? ? ? ? 0 0 read/write ? ? ? ? ? ? r/w r/w .7-.4 not used for s3c9228/p9228 .1 p3.1's interrupt state setting bit 0 falling edge interrupt 1 rising edge interrupt .0 p3.0's interrupt state setting bit 0 falling edge interrupt 1 rising edge interrupt
control registers s3c9228/p9228 4- 28 p4conh ? port 4 control register high byte f9h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7-.6 p4.7/seg11 configuration bits 0 0 input mode 0 1 push-pull output 1 0 n-channel open-drain output 1 1 input, pull-up mode .5-.4 p4.6/seg10 configuration bits 0 0 input mode 0 1 push-pull output 1 0 n-channel open-drain output 1 1 input, pull-up mode .3-.2 p4.5/seg9 configuration bits 0 0 input mode 0 1 push-pull output 1 0 n-channel open-drain output 1 1 input, pull-up mode .1-.0 p4.4/seg8 configuration bits 0 0 input mode 0 1 push-pull output 1 0 n-channel open-drain output 1 1 input, pull-up mode
s3c9228/p9228 control registers 4- 29 p4conl ?port 4 control register low byte fah bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7-.6 p4.3/seg7 configuration bits 0 0 input mode 0 1 push-pull output 1 0 n-channel open-drain output 1 1 input, pull-up mode .5-.4 p4.2/seg6 configuration bits 0 0 input mode 0 1 push-pull output 1 0 n-channel open-drain output 1 1 input, pull-up mode .3-.2 p4.1/seg5 configuration bits 0 0 input mode 0 1 push-pull output 1 0 n-channel open-drain output 1 1 input, pull-up mode .1-.0 p4.0/seg4 configuration bits 0 0 input mode 0 1 push-pull output 1 0 n-channel open-drain output 1 1 input, pull-up mode
control registers s3c9228/p9228 4- 30 p5conh ? port 5 control register high byte fbh bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 -.6 p5.7/seg19/com4 configuration bits 0 0 input mode 0 1 push-pull output 1 0 n-channel open-drain output 1 1 input, pull-up mode .5-.4 p5.6/seg18/com5 configuration bits 0 0 input mode 0 1 push-pull output 1 0 n-channel open-drain output 1 1 input, pull-up mode .3-.2 p5.5/seg17/com6 configuration bits 0 0 input mode 0 1 push-pull output 1 0 n-channel open-drain output 1 1 input, pull-up mode .1-.0 p5.4/seg16/com7 configuration bits 0 0 input mode 0 1 push-pull output 1 0 n-channel open-drain output 1 1 input, pull-up mode
s3c9228/p9228 control registers 4- 31 p5conl ? port 5 control register low byte fch bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 -.6 p5.3/seg15 configuration bits 0 0 input mode 0 1 push-pull output 1 0 n-channel open-drain output 1 1 input, pull-up mode .5-.4 p5.2/seg14 configuration bits 0 0 input mode 0 1 push-pull output 1 0 n-channel open-drain output 1 1 input, pull-up mode .3-.2 p5.1/seg13 configuration bits 0 0 input mode 0 1 push-pull output 1 0 n-channel open-drain output 1 1 input, pull-up mode .1-.0 p5.0/seg12 configuration bits 0 0 input mode 0 1 push-pull output 1 0 n-channel open-drain output 1 1 input, pull-up mode
control registers s3c9228/p9228 4- 32 p6con ? port 6 control register high byte fdh bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 -.6 p6.3/com0 configuration bits 0 0 input mode 0 1 push-pull output 1 0 n-channel open-drain output 1 1 input, pull-up mode .5-.4 p6.2/com1 configuration bits 0 0 input mode 0 1 push-pull output 1 0 n-channel open-drain output 1 1 input, pull-up mode .3-.2 p6.1/com2 configuration bits 0 0 input mode 0 1 push-pull output 1 0 n-channel open-drain output 1 1 input, pull-up mode .1-.0 p6.0/com3 configuration bits 0 0 input mode 0 1 push-pull output 1 0 n-channel open-drain output 1 1 input, pull-up mode
s3c9228/p9228 control registers 4- 33 siocon ? sio control register e1 h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 ? read/write r/w r/w r/w r/w r/w r/w r/w ? .7 sio shift clock selection bit 0 internal clock ( p.s clock) 1 external clock (sck) .6 data direction control bit 0 msb-first mode 1 lsb-first mode . 5 sio mode selection bit 0 receive-only mode 1 transmit/receive mode . 4 shift clock edge selection bit 0 tx at falling edges, rx at rising edges 1 tx at rising edges, rx at falling edges .3 sio counter clear and shift start bit 0 no action 1 clear 3-bit counter and start shifting . 2 sio shift operation enable bit 0 disable shifter and clock counter 1 enable shifter and clock counter . 1 sio interrupt enable bit 0 disable sio interrupt 1 enable sio interrupt . 0 not used for s3c9228/p9228
control registers s3c9228/p9228 4- 34 stpcon ? stop control register e0h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 stop control bits 1 0 1 0 0 1 0 1 enable stop instruction other values disable stop instruction note: before executing the stop instruction, the stpcon register must be set to "10100101b". otherwise the stop instruction will not execute.
s3c9228/p9228 control registers 4- 35 sym ? system mode register dfh bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? ? ? 0 0 0 0 read/write ? ? ? ? r/w r/w r/w r/w .7-.4 not used for s3c9228/p9228 .3 global interrupt enable bit 0 g lobal interrupt processing disable (di instruction) 1 g lobal interrupt processing enable (ei instruction) .2- .0 page selection bits 0 0 0 page 0 0 0 1 page 1 other values not available
control registers s3c9228/p9228 4- 36 t a con ? timer 1/a control register bb h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 ? read/write r/w r/w r/w r/w r/w r/w r/w ? .7 timer 1 mode selection bit 0 two 8-bit timers mode (timer a/b) 1 one 16-bit timer mode (timer 1) .6-.4 timer 1/a clock selection bits 0 0 0 fxx/512 0 0 1 fxx/256 0 1 0 fxx/64 0 1 1 fxx/8 1 0 0 fxx (system clock) 1 0 1 fxt (sub clock) 1 1 0 t1clk (external clock) 1 1 1 not available .3 timer 1/a counter clear bit 0 no effect 1 clear the timer 1/a counter (when write) .2 timer 1/a counter enable bit 0 disable counting operation 1 enable counting operation .1 timer 1/a interrupt enable bit 0 disable interrupt 1 enable interrupt .0 bit 0 not used for s3c9228/p9228
s3c9228/p9228 control registers 4- 37 t b con ? timer b control register ba h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? 0 0 0 0 0 0 ? read/write ? r/w r/w r/w r/w r/w r/w ? .7 not used for s3c9228/p9228 .6-.4 timer b clock selection bits 0 0 0 fxx/512 0 0 1 fxx/256 0 1 0 fxx/64 0 1 1 fxx/8 1 0 0 fxx (system clock) 1 0 1 fxt (sub clock) .3 timer b counter clear bit 0 no effect 1 clear the timer b counter (when write) .2 timer b counter enable bit 0 disable counting operation 1 enable counting operation .1 timer b interrupt enable bit 0 disable interrupt 1 enable interrupt .0 not used for s3c9228/p9228
control registers s3c9228/p9228 4- 38 wtcon ? watch timer control register da h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 ? read/write r/w r/w r/w r/w r/w r/w r/w ? .7 watch timer clock selection bit 0 select main clock divided by 2 7 (fx/128) 1 select sub clock ( fxt) .6 watch timer interrupt enable bit 0 disable watch timer interrupt 1 enable watch timer interrupt .5-.4 buzzer signal selection bits 0 0 0.5 khz 0 1 1 khz 1 0 2 khz 1 1 4 khz .3-.2 watch timer speed selection bits 0 0 set watch timer interrupt to 1s 0 1 set watch timer interrupt to 0.5s 1 0 set watch timer interrupt to 0.25s 1 1 set watch timer interrupt to 3.91ms .1 watch timer enable bit 0 disable watch timer; clear frequency dividing circuits 1 enable watch timer .0 not used for s3c9228/p9228
s3c9228/p9228 interrupt structure 5- 1 5 interrupt structure overview the sam88rcri interrupt structure has two basic components: a vector, and sources. the number of interrupt sources can be serviced through a interrupt vector which is assigned in rom address 0000h?0001h. sources vector s1 s2 s3 sn 0000h 0001h notes: 1. the sam88rcri interrupt has only one vector address (0000h-0001h). 2. the number of sn value is expandable. figure 5- 1 . s3c9 -series interrupt type interrupt processing control points interrupt processing can be controlled in two ways: globally, or by specific interrupt level and source. the system- level control points in the interrupt structure are therefore: ? global interrupt enable and disable (by ei and di instructions) ? interrupt source en able and disable settings in the corresponding peripheral control register(s) enable/disable interrupt instructions (ei, di) the system mode register, sym (dfh), is used to enable and disable interrupt processing. sym.3 is the enable and disable bit for global interrupt processing, which you can set by modifying sym.3 . an enable interrupt (ei) instruction must be included in the initialization routine that follows a reset operation in order to enable interrupt processing. al though you can manipulate sym.3 directly to enable and disable interrupts during normal operation, we recommend that you use the ei and di instructions for this purpose.
interrupt structure s3c9228/p9228 5- 2 interrupt pending function types when the interrupt service routine has executed, the application program's service routine must clear the appropriate pending bit before the return from interrupt subroutine (iret) occurs. interrupt priority because there is not a interrupt priority register in sam87 rc r i , the order of service is determined by a sequence of source which is executed in interrupt service routine. s r q interrupt pending register global interrupt control (ei, di instruction) vector interrupt cycle interrpt priority is determind by software polling method "ei" instruction execution reset source interrupts source interrupt enable figure 5- 2 . interrupt function diagram
s3c9228/p9228 interrupt structure 5- 3 interrupt source service sequence the interrupt request polling and servicing sequence is as follows: 1. a source generates an interrupt request by setting the interrupt request pending bit to "1". 2. the cpu generates an interrupt acknowledge signal. 3. the service routine starts and the source's pending flag is cleared to "0" by software. 4. interrupt priority must be determined by software polling method. interrupt service routines before an interrupt request can be serviced, the following conditions must be met: ? interrupt proce ssing must be enabled (ei, sym.3 = "1") ? interrupt must be enabled at the interrupt's source (peripheral control register) if all of the above conditions are met, the interrupt request is acknowledged at the end of the instruction cycle. the cpu then initiates an interrupt machine cycle that completes the following processing sequence: 1. reset (clear to "0") the global interrupt enable bit in the sym register (di, sym. 3 = "0") to disable all subsequent interrupts. 2. save the program counter and status flags to stack. 3. branch to the interrupt vector to fetch the service routine's address. 4. pass control to the interrupt service ro utine. when the interrupt service routine is completed, an interrupt return instruction (iret) occurs. the iret restores the pc and status flags and sets sym.3 to "1"(ei), allowing the cpu to process the next interrupt request. generating interrupt vector addresses the interrupt vector area in the rom contains the address of the interrupt service routine. vectored interrupt processing follows this sequence: 1. push the program counter's low-byte value to s tack. 2. push the program counter's high-byte value to stack. 3. push the flags register values to stack. 4. fetch the service routine's high-byte address from the vector address 0000h. 5. fetch the service routine's low-byte address from the vector address 0001h. 6. branch to the service routine specified by the 16-bit vector address.
interrupt structure s3c9228/p9228 5- 4 s3c9228/p9228 interrupt structure the s3c9228/p9228 microcontroller has fourteen peripheral interrupt sources: ? timer 1/a interr upt ? timer b interrupt ? sio interrupt ? watch timer interrupt ? four external interrupts for port 0 ? four external interrupts for port 1 ? two external interrupts for port 3
s3c9228/p9228 interrupt structure 5- 5 sym.3 (ei, di) p0int.0 p0.0 external interript p0int.1 p0.1 external interript p0.3 external interript p0.2 external interript p0int.2 p0int.3 intpnd1.0 intpnd1.1 intpnd1.2 intpnd1.3 p1.0 external interript p1int.0 p1.2 external interript p1.3 external interrupt p1.1 external interript p1int.1 p1int.2 p1int.3 tacon.1 tbcon.1 intpnd1.4 intpnd1.5 intpnd1.6 intpnd1.7 intpnd2.0 intpnd2.1 siocon.1 wtcon.1 p3int.0 p3int.1 intpnd2.2 intpnd2.3 intpnd2.4 intpnd2.5 0000h 0001h vector enable/disable pending sources timer b interrupt timer 1/a interrupt watch timer interrupt p3.0 interrupt sio interrupt p3.1 interrupt figure 5- 3 . s3c9228/p9228 interrupt structure
interrupt structure s3c9228/p9228 5- 6 programming tip ? how to clear an interrupt pending bit as the following examples are shown, a load instruction should be used to clear an interrupt pending bit. examples: 1. ld intpnd1, #11111011b ; clear p0.2's interrupt pending bit iret 2. l d intpnd2, #11110111b ; clear watch timer interrupt pending bit iret
s3c9228/p9228 s am8 8rc ri instruction set 6 - 1 6 sam8 8rc r i instruction set overview the sam88rcri instruction set is designed to support the large register file. it includes a full complement of 8- bit arithmetic and logic operations. there are 41 instructions. no special i/o instructions are necessary because i/o control and data registers are mapped directly into the register file. flexible instructions for bit addressing, rotate, and shift operations complete the powerful data manipulation capabilities of the sam88rcri instruction set. register addressing to access an individual register, an 8-bit address in the range 0-255 or the 4-bit address of a working register is specified. paired registers can be used to construct 1 6 -bit program memory or data memory addresses. for detailed information about register addressing, please refer to section 2, "address spaces". addressing modes there are six addressing modes: register (r), indirect register (ir), indexed (x), direct (da), relative (ra), and immediate (im). for detailed descriptions of these addressing modes, please refer to section 3, "addressing modes".
sam8 8 ri instruction set s3c9228/p9228 6 - 2 table 6- 1. instruction group summary mnemonic operands instruction load instructions clr dst clear ld dst,src load ldc dst,src load program memory lde dst,src load external data memory ldcd dst,src load program memory and decrement lded dst,src load external data memory and decrement ldci dst,src load program memory and increment ldei dst,src load external data memory and increment pop dst pop from stack push src push to stack arithmetic instructions adc dst,src add with carry add dst,src add cp dst,src compare dec dst decrement inc dst increment sbc dst,src subtract with carry sub dst,src subtract logic instructions and dst,src logical and com dst complement or dst,src logical or xor dst,src logical exclusive or
s3c9228/p9228 s am8 8rc ri instruction set 6 - 3 table 6- 1 . instruction group summary (continued) mnemonic operands instruction program control instructions call dst call procedure iret interrupt return jp cc,dst jump on condition code jp dst jump unconditional jr cc,dst jump relative on condition code ret return bit manipulation instructions tcm dst,src test complement under mask tm dst,src test under mask rotate and shift instructions rl dst rotate left rlc dst rotate left through carry rr dst rotate right rrc dst rotate right through carry sra dst shift right arithmetic cpu control instructions ccf complement carry flag di disable interrupts ei enable interrupts idle enter idle mode nop no operation rcf reset carry flag scf set carry flag stop enter stop mode
sam8 8 ri instruction set s3c9228/p9228 6 - 4 flags register (flags) the flags register contains eight bits that describe the current status of cpu operations. four of these bits, flags.4 ? flags.7, can be tested and used with conditional jump instructions; flags register can be set or reset by instructions as long as its outcome does not affect the flags, such as, load instruction. logical and arithmetic instructions such as, and, or, xor, add, and sub can affect the flags register. for example, the and instruction updates the zero, sign and overflow flags based on the outcome of the and instruction. if the and instruction uses the flags register as the destination, then simultaneously, two write will occur to the flags register producing an unpredictable result. .7 .6 .5 .4 .3 .2 .1 .0 lsb msb system flags register (flags) d5h, r/w not mapped carry flag (c) zero flag (z) sign flag (s) overflow flag (v) figure 6- 1 . system flags register (flags) flag descriptions overflow flag (flags.4, v) the v flag is set to "1" when the result of a two's-complement operation is greater than + 127 or less than ? 128. it is also cleared to "0" following logic operations. sign flag (flags.5, s) following arithmetic, logic, rotate, or shift operations, the sign bit identifies the state of the msb of the result. a logic zero indicates a positive number and a logic one indicates a negative number. zero flag (flags.6, z) for arithmetic and logic operations, the z flag is set to "1" if the result of the operation is zero. for operations that test register bits, and for shift and rotate operations, the z flag is set to "1" if the result is logic zero. carry flag (flags.7, c) the c flag is set to "1" if the result from an arithmetic operation generates a carry-out from or a borrow to the bit 7 position (msb). after rotate and shift operations, it contains the last value shifted out of the specified register. program instructions can set, clear, or complement the carry flag.
s3c9228/p9228 s am8 8rc ri instruction set 6 - 5 instruction set notation table 6- 2 . flag notation conventions flag description c carry flag z zero flag s sign flag v overflow flag 0 cleared to logic zero 1 set to logic one * set or cleared according to operation ? value is unaffected x value is undefined table 6- 3 . instruction set symbols symbol description dst destination operand src source operand @ indirect register address prefix pc program counter flags flags register (d5h) # immediate operand or register address prefix h hexadecimal number suffix d decimal number suffix b binary number suffix opc opcode
sam8 8 ri instruction set s3c9228/p9228 6 - 6 table 6- 4 . instruction notation conventions notation description actual operand range cc condition code see list of condition codes in table 6- 6. r working register only rn (n = 0?15) rr working register pair rrp (p = 0, 2, 4, ..., 14) r register or working register reg or rn ( reg = 0?255, n = 0?15) rr register pair or working register pair reg or rrp ( reg = 0?254, even number only, where p = 0, 2, ..., 14) ir indirect working register only @ rn (n = 0?15) ir indirect register or indirect working register @ rn or @ reg ( reg = 0?255, n = 0?15) irr indirect working register pair only @ rrp (p = 0, 2, ..., 14) irr indirect register pair or indirect working register pair @ rrp or @ reg ( reg = 0?254, even only, where p = 0, 2, ..., 14) x indexed addressing mode # reg[ rn] ( reg = 0?255, n = 0?15) xs indexed (short offset) addressing mode # addr[ rrp] ( addr = range ?128 to +127, where p = 0, 2, ..., 14) xl indexed (long offset) addressing mode # addr [ rrp] ( addr = range 0?8191, where p = 0, 2, ..., 14) da direct addressing mode addr ( addr = range 0?8191) ra relative addressing mode addr ( addr = number in the range +127 to ?128 that is an offset relative to the address of the next instruction) im immediate addressing mode #data (data = 0?255)
s3c9228/p9228 s am8 8rc ri instruction set 6 - 7 table 6- 5 . opcode quick reference opcode map lower nibble (hex) ? 0 1 2 3 4 5 6 7 u 0 dec r1 dec ir1 add r1,r2 add r1,ir2 add r2,r1 add ir2,r1 add r1,im p 1 rlc r1 rlc ir1 adc r1,r2 adc r1,ir2 adc r2,r1 adc ir2,r1 adc r1,im p 2 inc r1 inc ir1 sub r1,r2 sub r1,ir2 sub r2,r1 sub ir2,r1 sub r1,im e 3 jp irr1 sbc r1,r2 sbc r1,ir2 sbc r2,r1 sbc ir2,r1 sbc r1,im r 4 or r1,r2 or r1,ir2 or r2,r1 or ir2,r1 or r1,im 5 pop r1 pop ir1 and r1,r2 and r1,ir2 and r2,r1 and ir2,r1 and r1,im n 6 com r1 com ir1 tcm r1,r2 tcm r1,ir2 tcm r2,r1 tcm ir2,r1 tcm r1,im i 7 push r2 push ir2 tm r1,r2 tm r1,ir2 tm r2,r1 tm ir2,r1 tm r1,im b 8 ld r1, x, r2 b 9 rl r1 rl ir1 ld r2, x, r1 l a cp r1,r2 cp r1,ir2 cp r2,r1 cp ir2,r1 cp r1,im ldc r1, irr2, xl e b clr r1 clr ir1 xor r1,r2 xor r1,ir2 xor r2,r1 xor ir2,r1 xor r1,im ldc r2, irr2, xl c rrc r1 rrc ir1 ldc r1,irr2 ld r1, ir2 h d sra r1 sra ir1 ldc r2,irr1 ld ir1,im ld ir1, r2 e e rr r1 rr ir1 ldcd r1,irr2 ldci r1,irr2 ld r2,r1 ld r2,ir1 ld r1,im ldc r1, irr2, xs x f call irr1 ld ir2,r1 call da1 ldc r2, irr1, xs
sam8 8 ri instruction set s3c9228/p9228 6 - 8 table 6- 5 . opcode quick reference (continued) opcode map lower nibble (hex) ? 8 9 a b c d e f u 0 ld r1,r2 ld r2,r1 jr cc,ra ld r1,im jp cc,da inc r1 p 1 p 2 e 3 r 4 5 n 6 idle i 7 stop b 8 di b 9 ei l a re t e b iret c rcf h d scf e e ccf x f ld r1,r2 ld r2,r1 jr cc,ra ld r1,im jp cc,da inc r1 nop
s3c9228/p9228 s am8 8rc ri instruction set 6 - 9 condition codes the opcode of a conditional jump always contains a 4-bit field called the condition code (cc). this specifies under which conditions it is to execute the jump. for example, a conditional jump with the condition code for "equal" after a compare operation only jumps if the two operands are equal. condition codes are listed in table 6- 6. the carry (c), zero (z), sign (s), and overflow (v) flags are used to control the operation of conditional jump instructions. table 6- 6 . condition codes binary mnemonic description flags set 0000 f always false ? 1000 t always true ? 0111 (1) c carry c = 1 1111 (1) nc no carry c = 0 0110 (1) z zero z = 1 1110 (1) nz not zero z = 0 1101 pl plus s = 0 0101 mi minus s = 1 0100 ov overflow v = 1 1100 nov no overflow v = 0 0110 (1) eq equal z = 1 1110 (1) ne not equal z = 0 1001 ge greater than or equal (s xor v) = 0 0001 lt less than (s xor v) = 1 1010 gt greater than (z or (s xor v)) = 0 0010 le less than or equal (z or (s xor v)) = 1 1111 (1) uge unsigned greater than or equal c = 0 0111 (1) ult unsigned less than c = 1 1011 ugt unsigned greater than (c = 0 and z = 0) = 1 0011 ule unsigned less than or equal (c or z) = 1 notes: 1. i ndicate condition codes that are related to two different mnemonics but which test the same flag. for exa mple, z and eq are both true if the zero flag (z) is set, but after an add instruction, z would probably be used; after a cp instruction, however, eq would probably be used. 2. for operations involving unsigned numbers, the special condition codes uge, ult, ugt, and ule must be used.
sam8 8 ri instruction set s3c9228/p9228 6 - 10 instruction descriptions this section contains detailed information and programming examples for each instruction in the sam88rcri instruction set. information is arranged in a consistent format for improved readability and for fast referencing. the following information is included in each instruction description: ? instruction name (mnemonic) ? full instruction name ? source/destination format of the instruction operand ? shorthand notation of the instruction's operation ? textual description of the instruction's effect ? specific flag settings affected by the instruction ? detailed description of the instruction's format, execution time, and addressing mode(s) ? programming example(s) explaining how to use the instruction
s3c9228/p9228 s am8 8rc ri instruction set 6 - 11 adc ? add with carry adc dst,src operation: dst dst + src + c the source operand, along with the setting of the carry flag, is added to the destination operand and the sum is stored in the destination. the contents of the source are unaffected. two's- complement addition is performed. in multiple precision arithmetic, this instruction permits the carry from the addition of low-order operands to be carried into the addition of high-order operands. flags: c: set if there is a carry from the most significant bit of the result; cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurs, that is, if both operands are of the same sign and the result is of the opposite sign; cleared otherwise. d: always cleared to "0". h: set if there is a carry from the most significant bit of the low-order four bits of the result; cleared otherwise. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 12 r r 6 13 r lr opc src dst 3 6 14 r r 6 15 r ir opc dst src 3 6 16 r im examples: given: r1 = 10h, r2 = 03h, c flag = "1", register 01h = 20h, register 02h = 03h, and register 03h = 0ah: adc r1,r2 ? r1 = 14h, r2 = 03h adc r1,@r2 ? r1 = 1bh, r2 = 03h adc 01h,02h ? register 01h = 24h, register 02h = 03h adc 01h,@02h ? register 01h = 2bh, register 02h = 03h adc 01h,#11h ? register 01h = 32h in the first example, destination register r1 contains the value 10h, the carry flag is set to "1", and the source working register r2 contains the value 03h. the statement "adc r1,r2" adds 03h and the carry flag value ("1") to the destination value 10h, leaving 14h in register r1.
sam8 8 ri instruction set s3c9228/p9228 6 - 12 add ? add add dst,src operation: dst dst + src the source operand is added to the destination operand and the sum is stored in the destination. the contents of the source are unaffected. two's-complement addition is performed. flags: c: set if there is a carry from the most significant bit of the result; cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred, that is, if both operands are of the same sign and the result is of the opposite sign; cleared otherwise. d: always cleared to "0". h: set if a carry from the low-order nibble occurred. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 02 r r 6 03 r lr opc src dst 3 6 04 r r 6 05 r ir opc dst src 3 6 06 r im examples: given: r1 = 12h, r2 = 03h, register 01h = 21h, register 02h = 03h, register 03h = 0ah: add r1,r2 ? r1 = 15h, r2 = 03h add r1,@r2 ? r1 = 1ch, r2 = 03h add 01h,02h ? register 01h = 24h, register 02h = 03h add 01h,@02h ? register 01h = 2bh, register 02h = 0 3h add 01h,#25h ? register 01h = 46h in the first example, destination working register r1 contains 12h and the source working register r2 contains 03h. the statement "add r1,r2" adds 03h to 12h, leaving the value 15h in register r1.
s3c9228/p9228 s am8 8rc ri instruction set 6 - 13 and ? logical and and dst,src operation: dst dst and src the source operand is logically anded with the destination operand. the result is stored in the destination. the and operation results in a "1" bit being stored whenever the corresponding bits in the two operands are both logic ones; otherwise a "0" bit value is stored. the contents of the source are unaffected. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always cleared to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 52 r r 6 53 r lr opc src dst 3 6 54 r r 6 55 r ir opc dst src 3 6 56 r im examples: given: r1 = 12h, r2 = 03h, register 01h = 21h, register 02h = 03h, register 03h = 0ah: and r1,r2 ? r1 = 02h, r2 = 03h and r1,@r2 ? r1 = 02h, r2 = 03h and 01h,02h ? register 01h = 01h, register 02h = 03h and 01h,@02h ? register 01h = 00h, register 02h = 03h and 01h,#25h ? register 01h = 21h in the first example, destination working register r1 contains the value 12h and the source working register r2 contains 03h. the statement "and r1,r2" logically ands the source operand 03h with the destination operand value 12h, leaving the value 02h in register r1.
sam8 8 ri instruction set s3c9228/p9228 6 - 14 call ? call procedure call dst operation: sp sp ? 1 @sp pcl sp sp ?1 @sp pch pc dst the current contents of the program counter are pushed onto the top of the stack. the program counter value used is the address of the first instruction following the call instruction. the specified destination address is then loaded into the program counter and points to the first instruction of a procedure. at the end of the procedure the return instruction (ret) can be used to return to the original program flow. ret pops the top of the stack back into the program counter. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst opc dst 3 14 f6 da opc dst 2 12 f4 irr examples: given: r0 = 15h, r1 = 21h, pc = 1a47h, and sp = 0b2h: call 1521h ? sp = 0b0h (memory locations 00h = 1ah, 01h = 4ah, where 4ah is the address that follows the instruction.) call @rr0 ? sp = 0b0h (00h = 1ah, 01h = 49h) in the first example, if the program counter value is 1a47h and the stack pointer contains the value 0b2h, the statement "call 1521h" pushes the current pc value onto the top of the stack. the stack pointer now points to memory location 00h. the pc is then loaded with the value 1521h, the address of the first instruction in the program sequence to be executed. if the contents of the program counter and stack pointer are the same as in the first example, the statement "call @rr0" produces the same result except that the 49h is stored in stack location 01h (because the two-byte instruction format was used). the pc is then loaded with the value 1521h, the address of the first instruction in the program sequence to be executed.
s3c9228/p9228 s am8 8rc ri instruction set 6 - 15 ccf ? complement carry flag ccf operation: c not c the carry flag (c) is complemented. if c = "1", the value of the carry flag is changed to logic zero; if c = "0", the value of the carry flag is changed to logic one. flags: c: complemented. no other flags are affected. format: bytes cycles opcode (hex) opc 1 4 ef example: given: the carry flag = "0": ccf if the carry flag = "0", the ccf instruction complements it in the flags register (0d5h), changing its value from logic zero to logic one.
sam8 8 ri instruction set s3c9228/p9228 6 - 16 clr ? clear clr dst operation: dst "0" the destination location is cleared to "0". flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 b0 r 4 b1 ir examples: given: register 00h = 4fh, register 01h = 02h, and register 02h = 5eh: clr 00h ? register 00h = 00h clr @01h ? register 01h = 02h, register 02h = 00h in register (r) addressing mode, the statement "clr 00h" clears the destination register 00h value to 00h. in the second example, the statement "clr @01h" uses indirect register (ir) addressing mode to clear the 02h register value to 00h.
s3c9228/p9228 s am8 8rc ri instruction set 6 - 17 com ? complement com dst operation: dst not dst the contents of the destination location are complemented (one's complement); all "1s" are changed to "0s", and vice-versa. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always reset to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 60 r 4 61 ir examples: given: r1 = 07h and register 07h = 0f1h: com r1 ? r1 = 0f8h com @r1 ? r1 = 07h, register 07h = 0eh in the first example, destination working register r1 contains the value 07h (00000111b). the statement "com r1" complements all the bits in r1: all logic ones are changed to logic zeros, and vice-versa, leaving the value 0f8h (11111000b). in the second example, indirect register (ir) addressing mode is used to complement the value of destination register 07h (11110001b), leaving the new value 0eh (00001110b).
sam8 8 ri instruction set s3c9228/p9228 6 - 18 cp ? compare cp dst,src operation: dst ? src the source operand is compared to (subtracted from) the destination operand, and the appropriate flags are set accordingly. the contents of both operands are unaffected by the comparison. flags: c: set if a "borrow" occurred ( src > dst); cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the operands were of opposite signs and the sign of the result is of the same as the sign of the source operand; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 a2 r r 6 a3 r lr opc src dst 3 6 a4 r r 6 a5 r ir opc dst src 3 6 a6 r im examples: 1. given: r1 = 02h and r2 = 03h: cp r1,r2 ? set the c and s flags destination working register r1 contains the value 02h and source register r2 contains the value 03h. the statement "cp r1,r2" subtracts the r2 value (source/subtrahend) from the r1 value (destination/minuend). because a "borrow" occurs and the difference is negative, c and s are "1". 2. given: r1 = 05h and r2 = 0ah: cp r1,r2 jp uge,skip inc r1 skip ld r3,r1 in this example, destination working register r1 contains the value 05h which is less than the contents of the source working register r2 (0ah). the statement "cp r1,r2" generates c = "1" and the jp instruction does not jump to the skip location. after the statement "ld r3,r1" executes, the value 06h remains in working register r3.
s3c9228/p9228 s am8 8rc ri instruction set 6 - 19 dec ? decrement dec dst operation: dst dst ? 1 the contents of the destination operand are decremented by one. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if result is negative; cleared otherwise. v: set if arithmetic overflow occurred, that is, dst value is ?128(80h) and result value is +127(7fh); cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 00 r 4 01 ir examples: given: r1 = 03h and register 03h = 10h: dec r1 ? r1 = 02h dec @r1 ? register 03h = 0fh in the first example, if working register r1 contains the value 03h, the statement "dec r1" decrements the hexadecimal value by one, leaving the value 02h. in the second example, the statement "dec @r1" decrements the value 10h contained in the destination register 03h by one, leaving the value 0fh.
sam8 8 ri instruction set s3c9228/p9228 6 - 20 di ? disable interrupts di operation: sym (2) 0 bit zero of the system mode register, sym.2, is cleared to "0", globally disabling all interrupt processing. interrupt requests will continue to set their respective interrupt pending bits, but the cpu will not service them while interrupt processing is disabled. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 4 8f example: given: sym = 04h: di if the value of the sym register is 04h, the statement "di" leaves the new value 00h in the register and clears sym.2 to "0", disabling interrupt processing.
s3c9228/p9228 s am8 8rc ri instruction set 6 - 21 ei ? enable interrupts ei operation: sym (2) 1 an ei instruction sets bit 2 of the system mode register, sym.2 to "1". this allows interrupts to be serviced as they occur. if an interrupt's pending bit was set while interrupt processing was disabled (by executing a di instruction), it will be serviced when you execute the ei instruction. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 4 9f example: given: sym = 00h: ei if the sym register contains the value 00h, that is, if interrupts are currently disabled, the statement "ei" sets the sym register to 04h, enabling all interrupts (sym.2 is the enable bit for global interrupt processing) .
sam8 8 ri instruction set s3c9228/p9228 6 - 22 idle ? idle operation idle operation: the idle instruction stops the cpu clock while allowing system clock oscillation to continue. idle mode can be released by an interrupt request (irq) or an external reset operation. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc 1 4 6f ? ? example: the instruction idle stops the cpu clock but not the system clock.
s3c9228/p9228 s am8 8rc ri instruction set 6 - 23 inc ? increment inc dst operation: dst dst + 1 the contents of the destination operand are incremented by one. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred, that is dst value is +127(7fh) and result is ?128(80h); cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst dst | opc 1 4 re r r = 0 to f opc dst 2 4 20 r 4 21 ir examples: given: r0 = 1bh, register 00h = 0ch, and register 1bh = 0fh: inc r0 ? r0 = 1ch inc 00h ? register 00h = 0dh inc @r0 ? r0 = 1bh, register 01h = 10h in the first example, if destination working register r0 contains the value 1bh, the statement "inc r0" leaves the value 1ch in that same register. the next example shows the effect an inc instruction has on register 00h, assuming that it contains the value 0ch. in the third example, inc is used in indirect register (ir) addressing mode to increment the value of register 1bh from 0fh to 10h.
sam8 8 ri instruction set s3c9228/p9228 6 - 24 iret ? interrupt return iret iret operation: flags @sp sp sp + 1 pc @sp sp sp + 2 sym(2) 1 this instruction is used at the end of an interrupt service routine. it restores the flag register and the program counter. it also re-enables global interrupts. flags: all flags are restored to their original settings (that is, the settings before the interrupt occurred). format: iret (normal) bytes cycles opcode (hex) opc 1 6 bf
s3c9228/p9228 s am8 8rc ri instruction set 6 - 25 jp ? jump jp cc,dst (conditional) jp dst (unconditional) operation: if cc is true, pc dst the conditional jump instruction transfers program control to the destination address if the condition specified by the condition code (cc) is true; otherwise, the instruction following the jp instruction is executed. the unconditional jp simply replaces the contents of the pc with the contents of the specified register pair. control then passes to the statement addressed by the pc. flags: no flags are affected. format: (1) (2) bytes cycles opcode (hex) addr mode dst cc | opc dst 3 8 (3) ccd da cc = 0 to f opc dst 2 8 30 irr notes: 1. the 3-byte format is used for a conditional jump and the 2-byte format for an unconditional jump. 2. in the first byte of the three-byte instruction format (conditional jump), the condition code and the opcode are both four bits. examples: given: the carry flag (c) = "1", register 00 = 01h, and register 01 = 20h: jp c,label_w ? label_w = 1000h, pc = 1000h jp @00h ? pc = 0120h the first example shows a conditional jp. assuming that the carry flag is set to "1", the statement "jp c,label_w" replaces the contents of the pc with the value 1000h and transfers control to that location. had the carry flag not been set, control would then have passed to the statement immediately following the jp instruction. the second example shows an unconditional jp. the statement "jp @00" replaces the contents of the pc with the contents of the register pair 00h and 01h, leaving the value 0120h.
sam8 8 ri instruction set s3c9228/p9228 6 - 26 jr ? jump relative jr cc,dst operation: if cc is true, pc pc + dst if the condition specified by the condition code (cc) is true, the relative address is added to the program counter and control passes to the statement whose address is now in the program counter; otherwise, the instruction following the jr instruction is executed (see list of condition codes). the range of the relative address is +127, ?128, and the original value of the program counter is taken to be the address of the first instruction byte following the jr statement. flags: no flags are affected. format: (1) bytes cycles opcode (hex) addr mode dst cc | opc dst 2 6 (2) ccb ra cc = 0 to f note : in the first byte of the two-byte instruction format, the condition code and the opcode are each four bits. example: given: the carry flag = "1" and label_x = 1ff7h: jr c,label_x ? pc = 1ff7h if the carry flag is set (that is, if the condition code is true), the statement "jr c,label_x" will pass control to the statement whose address is now in the pc. otherwise, the program instruction following the jr would be executed.
s3c9228/p9228 s am8 8rc ri instruction set 6 - 27 ld ? load ld dst,src operation: dst src the contents of the source are loaded into the destination. the source's contents are unaffected. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src dst | opc src 2 4 rc r im 4 r8 r r src | opc dst 2 4 r9 r r r = 0 to f opc dst | src 2 4 c7 r lr 4 d7 ir r opc src dst 3 6 e4 r r 6 e5 r ir opc dst src 3 6 e6 r im 6 d6 ir im opc src dst 3 6 f5 ir r opc dst | src x 3 6 87 r x [r] opc src | dst x 3 6 97 x [r] r
sam8 8 ri instruction set s3c9228/p9228 6 - 28 ld ? load ld (continued) examples: given: r0 = 01h, r1 = 0ah, register 00h = 01h, register 01h = 20h, register 02h = 02h, loop = 30h, and register 3ah = 0ffh: ld r0,#10h ? r0 = 10h ld r0,01h ? r0 = 20h, register 01h = 20h ld 01h,r0 ? register 01h = 01h, r0 = 01h ld r1,@r0 ? r1 = 20h, r0 = 01h ld @r0,r1 ? r0 = 01h, r1 = 0ah, register 01h = 0ah ld 00h,01h ? register 00h = 20h, register 01h = 20h ld 02h,@00h ? register 02h = 20h, register 00h = 01h ld 00h,#0ah ? register 00h = 0ah ld @00h,#10h ? register 00h = 01h, register 01h = 10h ld @00h,02h ? register 00h = 01h, register 01h = 02, register 02h = 02h ld r0,#loop[r1] ? r0 = 0ffh, r1 = 0ah ld #loop[r0],r1 ? register 31h = 0ah, r0 = 01h, r1 = 0ah
s3c9228/p9228 s am8 8rc ri instruction set 6 - 29 ldc/lde ? load memory ldc/lde dst,src operation: dst src this instruction loads a byte from program or data memory into a working register or vice-versa. the source values are unaffected. ldc refers to program memory and lde to data memory. the assembler makes ' irr' or ' rr' values an even number for program memory and an odd number for data memory. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src 1. opc dst | src 2 10 c3 r irr 2. opc src | dst 2 10 d3 irr r 3. opc dst | src xs 3 12 e7 r xs [ rr] 4. opc src | dst xs 3 12 f7 xs [ rr] r 5. opc dst | src xl l xl h 4 14 a7 r xl [ rr] 6. opc src | dst xl l xl h 4 14 b7 xl [ rr] r 7. opc dst | 0000 da l da h 4 14 a7 r da 8. opc src | 0000 da l da h 4 14 b7 da r 9. opc dst | 0001 da l da h 4 14 a7 r da 10. opc src | 0001 da l da h 4 14 b7 da r notes: 1. the source ( src) or working register pair [ rr] for formats 5 and 6 cannot use register pair 0?1. 2. for formats 3 an d 4, the destination address 'xs [ rr]' and the source address 'xs [ rr]' are each one byte. 3. for formats 5 and 6, the destination address 'xl [ rr] and the source address 'xl [ rr]' are each two bytes. 4. the da and r source values for formats 7 and 8 are used to address program memory; the second set of values, used in formats 9 and 10, are used to address data memory.
sam8 8 ri instruction set s3c9228/p9228 6 - 30 ldc/lde ? load memory ldc/lde (continued) examples: given: r0 = 11h, r1 = 34h, r2 = 01h, r3 = 04h, r4 = 00h, r5 = 60h; program memory locations 0061 = aah, 0103h = 4fh, 0104h = 1a, 0105h = 6dh, and 1104h = 88h. external data memory locations 0061h = bbh, 0103h = 5fh, 0104h = 2ah, 0105h = 7dh, and 1104h = 98h: ldc r0,@rr2 ; r0 contents of program memory location 0104h ; r0 = 1ah, r2 = 01h, r3 = 04h lde r0,@rr2 ; r0 contents of external data memory location 0104h ; r0 = 2ah, r2 = 01h, r3 = 04h ldc * @rr2,r0 ; 11h (contents of r0) is loaded into program memory ; location 0104h (rr2), ; working registers r0, r2, r3 ? no change lde @rr2,r0 ; 11h (contents of r0) is loaded into external data memory ; location 0104h (rr2), ; working registers r0, r2, r3 ? no change ldc r0,#01h[rr4] ; r0 contents of program memory location 0061h ; (01h + rr4), ; r0 = aah, r2 = 00h, r3 = 60h lde r0,#01h[rr4] ; r0 contents of external data memory location 0061h ; (01h + rr4), r0 = bbh, r4 = 00h, r5 = 60h ldc (note) #01h[rr4],r0 ; 11h (contents of r0) is loaded into program me mory ; location 0061h (01h + 0060h) lde #01h[rr4],r0 ; 11h (contents of r0) is loaded into external data memory ; location 0061h (01h + 0060h) ldc r0,#1000h[rr2] ; r0 contents of program memory location 1104h ; (1000h + 0104h), r0 = 88h, r2 = 01h, r3 = 04h lde r0,#1000h[rr2] ; r0 contents of external data memory location 1104h ; (1000h + 0104h), r0 = 98h, r2 = 01h, r3 = 04h ldc r0,1104h ; r0 contents of program memory location 1104h, ; r0 = 88h lde r0,11 04h ; r0 contents of external data memory location 1104h, ; r0 = 98h ldc (note) 1105h,r0 ; 11h (contents of r0) is loaded into program memory ; location 1105h, (1105h) 11h lde 1105h,r0 ; 11h (contents of r0) is loaded into external data memory ; location 1105h, (1105h) 11h note: these instructions are not supported by masked rom type devices.
s3c9228/p9228 s am8 8rc ri instruction set 6 - 31 ldcd/lded ? load memory and decrement ldcd/lded dst,src operation: dst src rr rr ? 1 these instructions are used for user stacks or block transfers of data from program or data memory to the register file. the address of the memory location is specified by a working register pair. the contents of the source location are loaded into the destination location. the memory address is then decremented. the contents of the source are unaffected. ldcd references program memory and lded references external data memory. the assembler makes ? irr ? an even number for program memory and an odd number for data memory. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 10 e2 r irr examples: given: r6 = 10h, r7 = 33h, r8 = 12h, program memory location 1033h = 0cdh, and external data memory location 1033h = 0ddh: ldcd r8,@rr6 ; 0cdh (contents of program memory location 1033h) is ; loaded into r8 and rr6 is decremented by one ; r8 = 0cdh, r6 = 10h, r7 = 32h (rr6 ? rr6 - 1) lded r8,@rr6 ; 0ddh (contents of data memory location 103 3h) is ; loaded into r8 and rr6 is decremented by one ; (rr6 ? rr6 - 1) r8 = 0ddh, r6 = 10h, r7 = 32h
sam8 8 ri instruction set s3c9228/p9228 6 - 32 ldci/ldei ? load memory and increment ldci/ldei dst,src operation: dst src rr rr + 1 these instructions are used for user stacks or block transfers of data from program or data memory to the register file. the address of the memory location is specified by a working register pair. the contents of the source location are loaded into the destination location. the memory address is then incremented automatically. the contents of the source are unaffected. ldci refers to program memory and ldei refers to external data memory. the assembler makes ' irr' even for program memory and odd for data memory. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 10 e3 r irr examples: given: r6 = 10h, r7 = 33h, r8 = 12h, program memory locations 1033h = 0cdh and 1034h = 0c5h; external data memory locations 1033h = 0ddh and 1034h = 0d5h: ldci r8,@rr6 ; 0cdh (contents of program memory location 1033h) is ; loaded into r8 and rr6 is incremented by one ; (rr6 rr6 + 1) r8 = 0cdh, r6 = 10h, r7 = 34h ldei r8,@rr6 ; 0ddh (contents of data m emory location 1033h) is ; loaded into r8 and rr6 is incremented by one ; (rr6 rr6 + 1) r8 = 0ddh, r6 = 10h, r7 = 34h
s3c9228/p9228 s am8 8rc ri instruction set 6 - 33 nop ? no operation nop operation: no action is performed when the cpu executes this instruction. typic ally, one or more nops are executed in sequence in order to effect a timing delay of variable duration. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 4 ff example: when the instruction nop is encountered in a program, no operation occurs. instead, there is a delay in instruction execution time.
sam8 8 ri instruction set s3c9228/p9228 6 - 34 or ? logical or or dst,src operation: dst dst or src the source operand is logically ored with the destination operand and the result is stored in the destination. the contents of the source are unaffected. the or operation results in a "1" being stored whenever either of the corresponding bits in the two operands is a "1"; otherwise a "0" is stored. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always cleared to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 42 r r 6 43 r lr opc src dst 3 6 44 r r 6 45 r ir opc dst src 3 6 46 r im examples: given: r0 = 15h, r1 = 2ah, r2 = 01h, register 00h = 08h, register 01h = 37h, and register 08h = 8ah: or r0,r1 ? r0 = 3fh, r1 = 2ah or r0,@r2 ? r0 = 37h, r2 = 01h, register 01h = 37h or 00h,01h ? register 00h = 3fh, register 01h = 37h or 01h,@00h ? register 00h = 08h, register 01h = 0bfh or 00h,#02h ? register 00h = 0ah in the first example, if working register r0 contains the value 15h and reg ister r1 the value 2ah, the statement "or r0,r1" logical- ors the r0 and r1 register contents and stores the result (3fh) in destination register r0. the other examples show the use of the logical or instruction with the various addressing modes and formats.
s3c9228/p9228 s am8 8rc ri instruction set 6 - 35 pop ? pop from stack pop dst operation: dst @sp sp sp + 1 the contents of the location addressed by the stack pointer are loaded into the destination. the stack pointer is then incremented by one. flags: no flags affected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 8 50 r 8 51 ir examples: given: register 00h = 01h, register 01h = 1bh, sp (0d9h) = 0bbh, and stack register 0bbh = 55h: pop 00h ? register 00h = 55h, sp = 0bch pop @00h ? register 00h = 01h, register 01h = 55h, sp = 0bch in the first example, general register 00h contains the value 01h. the statement "pop 00h" loads the contents of location 0bbh (55h) into destination register 00h and then increments the stack pointer by one. register 00h then contains the value 55h and the sp points to location 0bch.
sam8 8 ri instruction set s3c9228/p9228 6 - 36 push ? push to stack push src operation: sp sp ? 1 @sp src a push instruction decrements the stack pointer value and loads the contents of the source ( src) into the location addressed by the decremented stack pointer. the operation then adds the new value to the top of the stack. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst opc src 2 8 70 r 8 71 ir examples: given: register 40h = 4fh, register 4fh = 0aah, sp = 0c0h: push 40h ? register 40h = 4fh, stack register 0bfh = 4fh, sp = 0bfh push @40h ? register 40h = 4fh, register 4fh = 0aah, stack register 0bfh = 0aah, sp = 0bfh in the first example, if the stack pointer contains the value 0c0h, and general register 40h the value 4fh, the statement "push 40h" decrements the stack pointer from 0c0 to 0bfh. it then loads the contents of register 40h into location 0bfh. register 0bfh then contains the value 4fh and sp points to location 0bfh.
s3c9228/p9228 s am8 8rc ri instruction set 6 - 37 rcf ? reset carry flag rcf rcf operation: c 0 the carry flag is cleared to logic zero, regardless of its previous value. flags: c: cleared to "0". no other flags are affected. format: bytes cycles opcode (hex) opc 1 4 cf example: given: c = "1" or "0": the instruction rcf clears the carry flag (c) to logic zero.
sam8 8 ri instruction set s3c9228/p9228 6 - 38 ret ? return ret operation: pc @sp sp sp + 2 the ret instruction is normally used to return to the previously executing procedure at the end of a procedure entered by a call instruction. the contents of the location addressed by the stack pointer are popped into the program counter. the next statement that is executed is the one that is addressed by the new program counter value. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 8 af example: given: sp = 0bch, (sp) = 101ah, and pc = 1234: ret ? pc = 101ah, sp = 0beh the statement "r et" pops the contents of stack pointer location 0bch (10h) into the high byte of the program counter. the stack pointer then pops the value in location 0bdh (1ah) into the pc's low byte and the instruction at location 101ah is executed. the stack pointer now points to memory location 0beh.
s3c9228/p9228 s am8 8rc ri instruction set 6 - 39 rl ? rotate left rl dst operation: c dst (7) dst (0) dst (7) dst (n + 1) dst (n), n = 0?6 the contents of the destination operand are rotated left one bit position. the initial value o f bit 7 is moved to the bit zero (lsb) position and also replaces the carry flag. c 7 0 flags: c: set if the bit rotated from the most significant bit position (bit 7) was "1". z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 90 r 4 91 ir examples: given: register 00h = 0aah, register 01h = 02h and register 02h = 17h: rl 00h ? register 00h = 55h, c = "1" rl @01h ? register 01h = 02h, register 02h = 2eh, c = "0" in the first example, if general register 00h contains the value 0aah (10101010b), the statement "rl 00h" rotates the 0aah value left one bit position, leaving the new value 55h (01010101b) and setting the carry and overflow flags.
sam8 8 ri instruction set s3c9228/p9228 6 - 40 rlc ? rotate left through carry rlc dst operation: dst (0) c c dst (7) dst (n + 1) dst (n), n = 0?6 the contents of the destination operand with the carry flag are rotated left one bit position. the initial value of bit 7 replaces the carry flag (c); the initial value of the carry flag replaces bit zero. c 7 0 flags: c: set if the bit rotated from the most significant bit position (bit 7) was "1". z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 10 r 4 11 ir examples: given: register 00h = 0aah, register 01h = 02h, and register 02h = 17h, c = "0": rlc 00h ? register 00h = 54h, c = "1" rlc @01h ? register 01h = 02h, register 02h = 2eh, c = "0" in the first example, if general register 00h has the value 0aah (10101010b), the statement "rlc 00h" rotates 0aah one bit position to the left. the initial value of bit 7 sets the carry flag and the initial value of the c flag replaces bit zero of register 00h, leaving the value 55h (01010101b). the msb of register 00h resets the carry flag to "1" and sets the overflow flag.
s3c9228/p9228 s am8 8rc ri instruction set 6 - 41 rr ? rotate right rr dst operation: c dst (0) dst (7) dst (0) dst (n) dst (n + 1), n = 0?6 the content s of the destination operand are rotated right one bit position. the initial value of bit zero (lsb) is moved to bit 7 (msb) and also replaces the carry flag (c). c 7 0 flags: c: set if the bit rotated from the least significant bit position (bit zero) was "1". z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 e0 r 4 e1 ir examples: given: register 00h = 31h, register 01h = 02h, and register 02h = 17h: rr 00h ? register 00h = 98h, c = "1" rr @01h ? register 01h = 02h, register 02h = 8bh, c = "1" in the first example, if general register 00h contains the value 31h (00110001b), the statement "rr 00h" rotates this value one bit position to the right. the initial value of bit zero is moved to bit 7, leaving the new value 98h (10011000b) in the destination register. the initial bit zero also resets the c flag to "1" and the sign flag and overflow flag are also set to "1".
sam8 8 ri instruction set s3c9228/p9228 6 - 42 rrc ? rotate right through carry rrc dst operation: dst (7) c c dst (0) dst (n) dst (n + 1), n = 0?6 the contents of the destination operand and the carry flag are rotated right one bit position. the initial value of bit zero (lsb) replaces the carry flag; the initial value of the carry flag replaces bit 7 (msb). c 7 0 flags: c: set if the bit rotated from the least significant bit position (bit zero) was "1". z: set if the result is "0" cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 c0 r 4 c1 ir examples: given: register 00h = 55h, register 01h = 02h, register 02h = 17h, and c = "0": rrc 00h ? register 00h = 2ah, c = "1" rrc @01h ? register 01h = 02h, register 02h = 0bh, c = "1" in the first example, if general register 00h contains the value 55h (01010101b), the statement "rrc 00h" rotates this value one bit position to the right. the initial value of bit zero ("1") replaces the carry flag and the initial value of the c f lag ("1") replaces bit 7. this leaves the new value 2ah (00101010b) in destination register 00h. the sign flag and overflow flag are both cleared to "0".
s3c9228/p9228 s am8 8rc ri instruction set 6 - 43 sbc ? subtract with carry sbc dst,src operation: dst dst ? src ? c the source operand, along with the current value of the carry flag, is subtracted from the destination operand and the result is stored in the destination. the contents of the source are unaffected. subtraction is performed by adding the two's-complement of the source operand to the destination operand. in multiple precision arithmetic, this instruction permits the carry ("borrow") from the subtraction of the low-order operands to be subtracted from the subtraction of high-order operands. flags: c: set if a borrow occurred ( src > dst); cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the operands were of opposite sign and the sign f the result is the same as the sign of the source; cleared otherwise. d: always set to "1". h: cleared if there is a carry from the most significant bit of the low-order four bits of the result; set otherwise, indicating a "borrow". format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 32 r r 6 33 r lr opc src dst 3 6 34 r r 6 35 r ir opc dst src 3 6 36 r im examples: given: r1 = 10h, r2 = 03h, c = "1", register 01h = 20h, register 02h = 03h, and reg ister 03h = 0ah: sbc r1,r2 ? r1 = 0ch, r2 = 03h sbc r1,@r2 ? r1 = 05h, r2 = 03h, register 03h = 0ah sbc 01h,02h ? register 01h = 1ch, register 02h = 03h sbc 01h,@02h ? register 01h = 15h,register 02h = 03h, register 03h = 0ah sbc 01h,#8ah ? register 01h = 95h; c, s, and v = "1" in the first example, if working register r1 contains the value 10h and register r2 the value 03h, the statement "sbc r1,r2" subtracts the source value (03h) and the c flag value ("1") from the destination (10h) and then stores the result (0ch) in register r1.
sam8 8 ri instruction set s3c9228/p9228 6 - 44 scf ? set carry flag scf operation: c 1 the carry flag (c) is set to logic one, regardless of its previous value. flags: c: set to "1". no other flags are affected. format: bytes cycles opcode (hex) opc 1 4 df example: the statement scf sets the carry flag to logic one.
s3c9228/p9228 s am8 8rc ri instruction set 6 - 45 sra ? shift right arithmetic sra dst operation: dst (7) dst (7) c dst (0) dst (n) dst (n + 1), n = 0?6 an arithmetic shift-right of one bit position is perform ed on the destination operand. bit zero (the lsb) replaces the carry flag. the value of bit 7 (the sign bit) is unchanged and is shifted into bit position 6. c 7 6 0 flags: c: set if the bit shifted from the lsb position (bit zero) was "1". z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: always cleared to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 d0 r 4 d1 ir examples: given: register 00h = 9ah, register 02h = 03h, register 03h = 0bch, and c = "1": sra 00h ? register 00h = 0cd, c = "0" sra @02h ? register 02h = 03h, register 03h = 0deh, c = "0" in the first example, if general register 00h contains the value 9ah (10011010b), the statement "sra 00h" shifts the bit values in register 00h right one bit position. bit zero ("0") clears the c flag and bit 7 ("1") is then shifted into the bit 6 position (bit 7 remains unchanged). this leaves the value 0cdh (11001101b) in destination register 00h.
sam8 8 ri instruction set s3c9228/p9228 6 - 46 stop ? stop operation stop operation: the stop instruction stops both the cpu clock and system clock and causes the microcontroller to enter stop mode. during stop mode, the contents of on-chip cpu registers, peripheral registers, and i/o port control and data registers are retained. stop mode can be released by an external reset operation or external interrupt input. for the reset operation, the reset pin must be held to low level until the required oscillation stabilization interval has elapsed. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc 1 4 7f ? ? example: the statement stop halts all microcontroller operations.
s3c9228/p9228 s am8 8rc ri instruction set 6 - 47 sub ? subtract sub dst,src operation: dst dst ? src the source operand is subtracted from the destination operand and the result is stored in the destination. the contents of the source are unaffected. subtraction is performed by adding the two's complement of the source operand to the destination operand. flags: c: set if a "borrow" occurred; cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the operands were of opposite signs and the sign of the result is of the same as the sign of the source operand; cleared otherwise. d: always set to "1". h: cleared if there is a carry from the most significant bit of the low-order four bits of the result; set otherwise indicating a "borrow". format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 22 r r 6 23 r lr opc src dst 3 6 24 r r 6 25 r ir opc dst src 3 6 26 r im examples: given: r1 = 12h, r2 = 03h, register 01h = 21h, register 02h = 03h, register 03h = 0ah: sub r1,r2 ? r1 = 0fh, r2 = 03h sub r1,@r2 ? r1 = 08h, r2 = 03h sub 01h,02h ? register 01h = 1eh, register 02h = 03h sub 01h,@02h ? register 01h = 17h, register 02h = 03h sub 01h,#90h ? register 01h = 91h; c, s, and v = "1" sub 01h,#65h ? register 01h = 0bch; c and s = "1", v = "0" in the first example, if working register r1 contains the value 12h and if register r2 contains the value 03h, the statement "sub r1,r2" subtracts the source value (03h) from the destination value (12h) and stores the result (0fh) in destination register r1.
sam8 8 ri instruction set s3c9228/p9228 6 - 48 tcm ? test complement under mask tcm dst,src operation: (not dst) and src thi s instruction tests selected bits in the destination operand for a logic one value. the bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask). the tcm statement complements the destination operand, which is then anded with the source mask. the zero (z) flag can then be checked to determine the result. the destination and source operands are unaffected. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always cleared to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 62 r r 6 63 r lr opc src dst 3 6 64 r r 6 65 r ir opc dst src 3 6 66 r im examples: given: r0 = 0c7h, r1 = 02h, r2 = 12h, register 00h = 2bh, register 01h = 02h, and register 02h = 23h: tcm r0,r1 ? r0 = 0c7h, r1 = 02h, z = "1" tcm r0,@r1 ? r0 = 0c7h, r1 = 02h, re gister 02h = 23h, z = "0" tcm 00h,01h ? register 00h = 2bh, register 01h = 02h, z = "1" tcm 00h,@01h ? register 00h = 2bh, register 01h = 02h, register 02h = 23h, z = "1" tcm 00h,#34 ? register 00h = 2bh, z = "0" in the first example, if working register r0 contains the value 0c7h (11000111b) and register r1 the value 02h (00000010b), the statement "tcm r0,r1" tests bit one in the destination register for a "1" value. because the mask value corresponds to the test bit, the z flag is set to logic one and can be tested to determine the result of the tcm operation.
s3c9228/p9228 s am8 8rc ri instruction set 6 - 49 tm ? test under mask tm dst,src operation: dst and src this instruction tests selected bits in the destination operand for a logic zero value. the bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask), which is anded with the destination operand. the zero (z) flag can then be checked to determine the result. the destination and source operands are unaffected. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always reset to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 72 r r 6 73 r lr opc src dst 3 6 74 r r 6 75 r ir opc dst src 3 6 76 r im examples: given: r0 = 0c7h, r1 = 02h, r2 = 18h, register 00h = 2bh, register 01h = 02h, and register 02h = 23h: tm r0,r1 ? r0 = 0c7h, r1 = 02h, z = "0" tm r0,@r1 ? r0 = 0c7h, r1 = 02h, register 02h = 23h, z = "0" tm 00h,01h ? register 00h = 2bh, register 01h = 02h, z = "0" tm 00h,@01h ? register 00h = 2bh, register 01h = 02h, register 02h = 23h, z = "0" tm 00h,#54h ? register 00h = 2bh, z = "1" in the first example, if working register r0 contains the value 0c7h (11000111b) and register r1 the value 02h (00000010b), the statement "tm r0,r1" tests bit one in the destination register for a "0" value. because the mask value does not match the test bit, the z flag is cleared to logic zero and can be tested to determine the result of the tm operation.
sam8 8 ri instruction set s3c9228/p9228 6 - 50 xor ? logical exclusive or xor dst,src operation: dst dst xor src the source operand is logically exclusive- ored with the destination operand and the result is stored in the destination. the exclusive-or operation results in a "1" bit being stored whenever the corresponding bits in the operands are different; otherwise, a "0" bit is stored. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always reset to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 b2 r r 6 b3 r lr opc src dst 3 6 b4 r r 6 b5 r ir opc dst src 3 6 b6 r im examples: given: r0 = 0c7h, r1 = 02h, r2 = 18h, register 00h = 2bh, register 01h = 02h, and register 02h = 23h: xor r0,r1 ? r0 = 0c5h, r1 = 02h xor r0,@r1 ? r0 = 0e4h, r1 = 02h, register 02h = 23h xor 00h,01h ? register 00h = 29h, register 01h = 02h xor 00h,@01h ? register 00h = 08h, register 01h = 02h, register 02h = 23h xor 00h,#54h ? register 00h = 7fh in the first example, if working register r0 contains the value 0c7h and if register r1 contains the value 02h, the statement "xor r0,r1" logically exclusive- ors the r1 value with the r0 value and stores the result (0c5h) in the destination register r0.
s3c9228/p9228 clock circuits 7- 1 7 clock circuits overview the s3c9228 microcontroller has two oscillator circuits: a main clock, and a sub clock circuit. the cpu and peripheral hardware operate on the system clock frequency supplied through these circuits. the maximum cpu clock frequency, is determined by clkcon register settings . system clock circuit the system clock circuit has the following components: ? c rystal , ceramic resonator , rc oscillation source (main clock only), or an external clock ? oscillator stop and wake-up functions ? programmable frequency divider for the cpu clock ( f xx divided by 1, 2, 8, or 16 ) ? clock circuit control register, clkcon ? oscillator control register, osccon cpu clock notation in this document, the following notation is used for descriptions of the cpu clock: fx main clock fxt sub clock fxx selected system clock
clock circuits s3c9 228/p9228 7- 2 main oscillator circuits x in x out figure 7-1. crystal/ceramic oscillator x in x out figure 7-2. external oscillator x in x out r figure 7-3. rc oscillator sub oscillator circuits xt in xt out 32.768 khz figure 7-4. crystal/ceramic oscillator xt in xt out figure 7-5. external oscillator
s3c9228/p9228 clock circuits 7- 3 clock status during power-down modes the two power-down modes, stop mode and idle mode, affect the system clock as follows: ? in stop mode, the main oscillator is halted. stop mode is released, and the oscillator started, by a reset operation, by an external interrupt, or by an internal interrupt if sub clock is selected as the clock source (when the fx is selected as system clock). ? in idle mode, the internal clock signal is gated away from the cpu, but continues to be supplied to the interrupt structure, timer a/b, and watch timer. idle mode is released by a reset or by an external or internal interrupts. 1/8-1/4096 frequency dividing circuit stop release main-system oscillator circuit selector 1 f x f x t stop sub-system oscillator circuit int osccon.0 osccon.3 osccon.2 1/1 1/16 1/2 1/8 selector 2 stpcon stop osc inst. f xx clkcon.4-.3 cpu stop watch timer basic timer timer/counters watch timer lcd controller a/d converter sio lcd controller figure 7-6. system clock circuit diagram
clock circuits s3c9 228/p9228 7- 4 system clock control register (clkcon) the system clock control register, clkcon, is located in address d4h. it is read/write addressable and has the following functions: ? oscillator irq wake-up function enable/disable ? oscillator frequency divide-by value clkcon register settings control whether or not an external interrupt can be used to trigger a stop mode release (this is called the ?irq wake-up? function). the irq ?wake-up? enable bit is clkcon.7. after a reset, the external interrupt oscillator wake-up function is enabled, the main oscillator is activated, and the f x /16 (the slowest clock speed) is selected as the cpu clock. if necessary, you can then increase the cpu clock speed to f x , f x /2, or f x /8 by setting the clkcon, and you can change system clock from main clock to sub clock by setting the osccon. system clock control register (clkcon) d4h, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb not used for s3c9228 (must keep always "0") divide-by selection bits for cpu clock frequency: 00 = f xx/16 01 = f xx/8 10 = f x x/2 11 = f xx oscillator irq wake-up enable bit: 0 = enable irq for main oscillator wake-up function in power down mode 1 = disable irq for main oscillator wake-up function in power down mode not used for s3c92228 (must keep always "0") figure 7-7. system clock control register (clkcon)
s3c9228/p9228 clock circuits 7- 5 oscillator control register (osccon) the oscillator control register, osccon, is located in address d3h. it is read/write addressable and has the following functions: ? system clock selection ? main oscillator control ? sub oscillator control osccon.0 register settings select main clock or sub clock as system clock. after a reset, main clock is selected for system clock because the reset value of osccon.0 is "0". the main oscillator can be stopped or run by setting osccon.3. the sub oscillator can be stopped or run by setting osccon.2. oscillator control register (osccon) d3h, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb not used for s3c9228 main oscillator control bit: 0 = main oscillator run 1 = main oscillator stop sub oscillator control bit: 0 = sub oscillator run 1 = sub oscillator stop not used for s3c9228 system clock selection bit: 0 = main oscillator select 1 = sub oscillator select figure 7-8. oscillator control register (osccon)
clock circuits s3c9 228/p9228 7- 6 switching the cpu clock data loadings in the oscillator control register, osccon, determine whether a main or a sub clock is selected as the cpu clock, and also how this frequency is to be divided by setting clkcon. this makes it possible to switch dynamically between main and sub clocks and to modify operating frequencies. osccon.0 select the main clock ( fx) or the sub clock ( fxt) for the system clock. osccon .3 start or stop main clock oscillation, and osccon.2 start or stop sub clock oscillation. clkcon.4?.3 control the frequency divider circuit, and divide the selected fxx clock by 1, 2, 8, or 16. for example, you are using the default system clock (normal operating mode and a main clock of fx/16) and you want to switch from the fx clock to a sub clock and to stop the main clock. to do this, you need to set osccon.0 to "1", take a delay, and osccon.3 to "1" sequently. this switches the clock from fx to fxt and stops main clock oscillation. the following steps must be taken to switch from a sub clock to the main clock: first, set osccon.3 to "0" to enable main system clock oscillation. then, after a certain number of machine cycles has elapsed, select the main clock by setting osccon.0 to "0". + + programming tip ? switching the cpu clock 1. this example shows how to change from the main clock to the sub clock: ma2sub or osccon,#01h ; switches to the sub clock call dly16 ; delay 16ms or osccon,#08h ; stop the main clock osc illation ret 2. this example shows how to change from sub clock to main clock: sub2ma and osccon,#0f7h ; start the main clock oscillation call dly16 ; delay 16 ms and osccon,#0feh ; switch to the main clock ret dly16 ld r0,#20h del nop dec r0 jr nz,del ret
s3c9228/p9228 clock circuits 7- 7 stop control register (stpcon) the stop control register, stpcon, is located in address e0h. it is read/write addressable and has the following functions: ? enable/disable stop instruction after a reset, the stop instruction is disabled, because the value of stpcon is "other values". if necessary, you can use the stop instruction by setting the value of stpcon to "10100101b". stop control register (stpcon) e0h, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb stop control bits: 10100101 = enable stop instruction other values = disable stop instruction figure 7-9. stop control register (stpcon) + + programming tip ? how to use stop instruction this example shows how to go stop mode when a main clock is selected as the system clock. ld stopcon,#1010010b ; enable stop instruction stop ; enter stop mode nop nop nop ; release stop mode ld stopcon,#00000000b ; disable stop instruction
clock circuits s3c9 228/p9228 7- 8 notes
s3c9228/p9228 reset reset and power-down 8- 1 8 reset reset and power-down system reset overview during a power-on reset, the voltage at v dd goes to high level and the reset pin is forced to low level. the reset signal is input through a schmitt trigger circuit where it is then synchronized with the cpu clock. this procedure brings s3c9228/p9228 into a known operating status. to allow time for internal cpu clock oscillation to stabilize, the reset pin must be held to low level for a minimum time interval after the power supply comes within tolerance. the minimum required oscillation stabilization time for a reset operation is 1 millisecond. whenever a reset occurs during normal operation (that is, when both v dd and reset are high level), the reset pin is forced low and the reset operation starts. all system and peripheral control registers are then reset to their default hardware values (see table 8-1). in summary, the following sequence of events occurs during a reset operation: ? all interrupts are disabled. ? the watchdog function (basic timer) is enabled. ? the p0.0?p0.3, p1, and p2.2?p2.3 are set to schmitt trigger input mode and all pull-up resistors are disabled for the i/o port pin circuits. ? peripheral control and data re gisters are disabled and reset to their default hardware values. ? the program counter (pc) is loaded with the program reset address in the rom, 0100h. ? when the programmed oscillation stabilization time interval has elapsed, the instruction stored in rom location 0100h (and 0101h) is fetched and executed. note to program the duration of the oscillation stabilization interval, you make the appropriate settings to the basic timer control register, btcon, before entering stop mode. also, if you do not want to use the basic timer watchdog function (which causes a system reset if a basic timer counter overflow occurs), you can disable it by writing '1010b' to the upper nibble of btcon.
reset reset and power-down s3c9228 /p9228 8- 2 power-down modes stop mode stop mode is invoked by the instruction stop. in stop mode, the operation of the cpu and main oscillator is halted. all peripherals which the main oscillator is selected as a clock source stop also because main oscillator stops. but the watch timer and lcd controller will not halted in stop mode if the sub clock is selected as watch timer clock source. the data stored in the internal register file are retained in stop mode. stop mode can be released in one of three ways: by a system reset, by an internal watch timer interrupt (when sub clock is selected as clock source of watch timer), or by an external interrupt. example: ld stopcon,#10100101b stop nop nop nop ld stopcon,#00000000b notes 1. do not use stop mode if you are using an external clock source because x in input must be restricted internally to v ss to reduce current leakage. 2. in application programs, a stop instruction must be immediately followed by at least three nop instructions. this ensures an adequate time interval for the clock to stabilize before the next instruction is executed. if three or more nop instructions are not used after stop instruction, leakage current could be flown because of the floating state in the internal bus. 3. to enable/disable stop instruction, the stopcon register should be written with 10100101b/other values before/after stop instruction. using reset to release stop mode stop mode is released when the reset signal goes active (low level): all system and peripheral control registers are reset to their default hardware values and the contents of all data registers are retained. when the programmed oscillation stabilization interval has elapsed, the cpu starts the system initialization routine by fetching the program instruction stored in rom location 0100h. using an external interrupt to release stop mode external interrupts can be used to release stop mode. for the s3c9228 microcontroller, we recommend using the int interrupt, p0, p1, and p3.
s3c9228/p9228 reset reset and power-down 8- 3 using an internal interrupt to release stop mode an internal interrupt, watch timer, can be used to release stop mode because the watch timer operates in stop mode if the clock source of watch timer is sub clock. if system clock is sub clock, you can't use any interrupts to release stop mode. that is, you had better use the idle instruction instead of stop one when sub clock is selected as the system clock. please note the following conditions for stop mode release: ? if you release stop mode using an internal or external interrupt, the current values in system and peripheral control registers are unchanged. ? if you use an internal or external interrupt for stop mode release, you can also program the duration of the oscillation stabilization interval. to do this, you must make the appropriate control and clock settings before entering stop mode. ? if you use an interrupt to release stop mode, the bit-pair setting for clkcon.4/clkcon.3 remains unchanged and the currently selected clock value is used. ? the internal or external interrupt is serviced when the stop mode release occurs. following the iret from the service routine, the instruction immediately following the one that initiated stop mode is executed. idle mode idle mode is invoked by the instruction idle ( opcode 6fh). in idle mode, cpu operations are halted while some peripherals remain active. during idle mode, the internal clock signal is gated away from the cpu and from all but the following peripherals, which remain active: ? interrupt logic ? basic timer ? timer 1 (timer a and b) ? watch timer ? lcd controller i/o port pins retain the mode (input or output) they had at the time idle mode was entered. idle mode release you can release idle mode in one of two ways: 1. execute a reset. all system and peripheral c ontrol registers are reset to their default values and the contents of all data registers are retained. the reset automatically selects the slowest clock (1/16) because of the hardware reset value for the clkcon register. if all external interrupts are masked in the imr register, a reset is the only way you can release idle mode. 2. activate any enabled interrupt ? internal or external. when you use an interrupt to release idle mode, the 2 -bit clkcon.4/clkcon.3 value remains unchanged, and the currently selected clock value is used. the interrupt is then serviced. when the return-from-interrupt condition (iret) occurs, the instruction immediately following the one which initiated idle mode is executed.
reset reset and power-down s3c9228 /p9228 8- 4 hardware reset reset values table 8-1 list the values for cpu and system registers, peripheral control registers, and peripheral data registers following a reset operation in normal operating mode. the following notation is used in these table to represent specific reset values: ? a "1" or a "0" shows the reset bit value as logic one or logic zero, respectively. ? an 'x' means that the bit value is undefined following reset . ? a dash ('?') means that the bit is either not used or not mapped. table 8-1. register values after reset reset register name mnemonic address bit values after reset reset dec hex 7 6 5 4 3 2 1 0 locations b8h?b9h are not mapped. timer b control register tbcon 202 bah ? 0 0 0 0 0 0 ? timer 1/a control register tacon 203 bbh 0 0 0 0 0 0 0 ? timer b data register tbdata 204 bch 1 1 1 1 1 1 1 1 timer a data register tadata 205 bdh 1 1 1 1 1 1 1 1 timer b counter tbcnt 206 beh 0 0 0 0 0 0 0 0 timer a counter tacnt 207 bfh 0 0 0 0 0 0 0 0 a/d converter control register adcon 208 d0h ? ? 0 0 0 0 0 0 a/d converter data register (high byte) addatah 209 d1h x x x x x x x x a/d converter data register (low byte) addatal 210 d2h ? ? ? ? ? ? x x oscillator control register osccon 211 d3h ? ? ? ? 0 0 ? 0 system clock control register clkcon 212 d4h 0 0 0 0 0 0 0 0 system flags register flags 213 d5h x x x x ? ? ? ? interrupt pending register 1 intpnd1 214 d6h 0 0 0 0 0 0 0 0 interrupt pending register 2 intpnd2 215 d7h ? ? 0 0 0 0 0 0 lcd port control register lopt 216 d8h ? 0 0 0 0 0 0 0 stack pointer sp 217 d9h x x x x x x x x watch timer control register wtcon 218 dah 0 0 0 0 0 0 0 ? locations dbh is not mapped. basic timer control register btcon 220 dch 0 0 0 0 0 0 0 0 basic timer counter btcnt 221 ddh 0 0 0 0 0 0 0 0 locations deh is not mapped.
s3c9228/p9228 reset reset and power-down 8- 5 table 8-1. register values after reset reset (continued) register name mnemonic address bit values after reset reset dec hex 7 6 5 4 3 2 1 0 system mode register sym 223 dfh ? ? ? ? 0 0 0 0 stop control register stpcon 224 e0h 0 0 0 0 0 0 0 0 sio control register siocon 225 e1h 0 0 0 0 0 0 0 ? sio data register siodata 226 e2h 0 0 0 0 0 0 0 0 sio prescaler register siops 227 e3h 0 0 0 0 0 0 0 0 port 0 data register p0 228 e4h 0 0 0 0 0 0 0 0 port 1 data register p1 229 e5h 0 0 0 0 0 0 0 0 port 2 data register p2 230 e6h 0 0 0 0 0 0 0 0 port 3 data register p3 231 e7h 0 0 0 0 0 0 0 0 port 4 data register p4 232 e8h 0 0 0 0 0 0 0 0 port 5 data register p5 233 e9h 0 0 0 0 0 0 0 0 port 6 data register p6 234 eah 0 0 0 0 0 0 0 0 port 0 control register p0con 235 ebh 0 0 0 0 0 0 0 0 port 0 pull-up resistors enable register p0pur 236 ech ? ? ? ? 0 0 0 0 port 0 interrupt control register p0int 237 edh ? ? ? ? 0 0 0 0 port 0 interrupt edge selection register p0edge 238 eeh ? ? ? ? 0 0 0 0 port 1 control register p1con 239 efh 0 0 0 0 0 0 0 0 port 1 pull-up resistors enable register p1pur 240 f0h ? ? ? ? 0 0 0 0 port 1 interrupt control register p1int 241 f1h ? ? ? ? 0 0 0 0 port 1 interrupt edge selection register p1edge 242 f2h ? ? ? ? 0 0 0 0 port 2 control register p2con 243 f3h 0 0 0 0 0 0 0 0 port 2 pull-up resistors enable register p2pur 244 f4h ? ? ? ? 0 0 0 0 port 3 control register p3con 245 f5h ? ? ? ? 0 0 0 0 port 3 pull-up resistors enable register p3pur 246 f6h ? ? ? ? ? ? 0 0 port 3 interrupt control register p3int 247 f7h ? ? ? ? ? ? 0 0 port 3 interrupt edge selection register p3edge 248 f8h ? ? ? ? ? ? 0 0 port 4 control register (high byte) p4conh 249 f9h 0 0 0 0 0 0 0 0 port 4 control register (high byte) p4conl 250 fah 0 0 0 0 0 0 0 0 port 5 control register (high byte) p5conh 251 fbh 0 0 0 0 0 0 0 0 port 5 control register (high byte) p5conl 252 fch 0 0 0 0 0 0 0 0 port 6 control register p6con 253 fdh 0 0 0 0 0 0 0 0 lcd mode register lmod 254 feh ? 0 0 0 0 0 0 0 location ffh is not mapped.
reset reset and power-down s3c9228 /p9228 8- 6 notes
s3c9228/p9228 i/o p orts 9- 1 9 i/o ports overview the s3c9228/p9228 microcontroller has seven bit-programmable i/o ports, p0-p6. port 0 is 6-bit port, port 1, port 2, and port 6 are 4-bit ports, port 3 is 2-bit port, and port 4 and port 5 are 8-bit ports. this gives a total of 36 i/o pins. each port can be flexibly configured to meet application design requirements. the cpu accesses ports by directly writing or reading port registers. no special i/o instructions are required. all ports of the s3c9228/p9228 except p0.4 and p0.5 can be configured to input or output mode. all lcd signal pins are shared with normal i/o ports. table 9-1 gives you a general overview of s3c9228 i/o port functions. table 9-1. s3c9228 port configuration overview port configuration options 0 1-bit programmable i/o port except p0.4 and p0.5. schmitt trigger input or push-pull, open-drain output and software assignable pull-ups. the p0.4 and p0.5 are only push-pull output ports. alternatively p0.0-p0.3 can be used as input for external interrupts int and can be used as taout, t1clk, and buz. 1 1-bit programmable i/o port. schmitt trigger input or push-pull, open-drain output and software assignable pull-ups. alternatively p1 can be used as input for external interrupts int and can be used as ad0-ad3. 2 1-bit programmable i/o port. schmitt trigger input or push-pull, open-drain output and software assignable pull-ups. alternatively p2.0 and p2.1 can be used as outputs for lcd segment signals and p2.0-p2.2 can be used as sck, so, and si. 3 1-bit programmable i/o port. schmitt trigger input or push-pull, open-drain output and software assignable pull-ups. alternatively p3 can be used as input for external interrupts intp and can be used as outputs for lcd segment signals. 4 1-bit programmable i/o port. input or push-pull, open-drain output and software assignable pull-ups. alternatively p4 can be used as outputs for lcd segment signals. 5 1-bit programmable i/o port. input or push-pull, open-drain output and software assignable pull-ups. alternatively p5.0-p5.3 can be used as outputs for lcd segment signals and p5.4-p5.7 can be used as outputs for lcd common or segment signals. 6 1-bit programmable i/o port. input or push-pull, open-drain output and software assignable pull-ups. alternatively p6 can be used as outputs for lcd common signals.
i/o ports s3c9228/p 9228 9- 2 port data registers table 9-2 gives you an overview of the register locations of all seven s3c9228 i/o port data registers. data registers for ports 1, 2, 3, 4, 5, and 6 have the general format shown in figure 9-1. table 9-2. port data register summary register name mnemonic decimal hex r/w port 0 data register p0 228 e4h r/w port 1 data register p1 229 e5h r/w port 2 data register p2 230 e6h r/w port 3 data register p3 231 e7h r/w port 4 data register p4 232 e8h r/w port 5 data register p5 233 e9h r/w port 6 data register p6 234 eah r/w msb s3c9228 i/o port data register format (n = 0-6) .7 .6 .5 .4 .3 .2 .1 .0 lsb pn.7 pn.6 pn.5 pn.4 pn.3 pn.2 pn.1 pn.0 figure 9-1. s3c9228 i/o port data register format
s3c9228/p9228 i/o p orts 9- 3 port 0 port 0 is an 6-bit i/o port with individually configurable pins. port 0 pins are accessed directly by writing or reading the port 0 data register, p0 at location e4h in page 0. p0.0-p0.3 can serve as inputs (with or without pull- up), as outputs (push-pull or open-drain) or you can be configured the following functions. ? low-nibble pins (p0.0-p0.3): taout,t1clk, buz, int ? high-nibble pins (p0.4-p0.5): push-pull output ports (only 44-qfp package) port 0 control register (p0con) port 0 has a 8-bit control register: p0con for p0.0-p0.3. a reset clears the p0con register to ?00h?, configuring pins to input mode. you use control register setting to select input or output mode (push-pull or open-drain) and enable the alternative functions. when programming this port, please remember that any alternative peripheral i/o function you configure using the port 0 control register must also be enabled in the associated peripheral module. port 0 pull-up resistor control register (p0pur) using the port 0 pull-up resistor control register, p0pur (ech, page 0), you can configure pull-up resistors to individual port 0 pins. port 0 interrupt enable, pending, and edge selection registers (p0int, intpnd1.3-.0, p0edge) to process external interrupts at the port 0 pins, three additional control registers are provided: the port 0 interrupt enable register p0int (edh, page 0), the port 0 interrupt pending bits intpnd1.3-.0 (d6h, page 0), and the port 0 interrupt edge selection register p0edge (eeh, page 0). the port 0 interrupt pending register bits lets you check for interrupt pending conditions and clear the pending condition when the interrupt service routine has been initiated. the application program detects interrupt requests by polling the intpnd1.3-.0 register at regular intervals. when the interrupt enable bit of any port 0 pin is "1", a rising or falling edge at that pin will generate an interrupt request. the corresponding intpnd1 bit is then automatically set to "1" and the irq level goes low to signal the cpu that an interrupt request is waiting. when the cpu acknowledges the interrupt request, application software must the clear the pending condition by writing a "0" to the corresponding intpnd1 bit.
i/o ports s3c9228/p 9228 9- 4 port 0 control register (p0con) ebh, page 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p0.3/buz (int) p0con bit-pair pin configuration settings: 00 01 10 11 n-channel open-drain output mode alternative function (taout, buz) p0.2 (int) p0.1/t1clk (int) p0.0/taout (int) push-pull output mode schmitt trigger input mode (t1clk) figure 9-2. port 0 control register (p0con) port 0 interrupt control register (p0int) edh, page 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb not used p0int bit configuration settings: 0 1 p0.3 (int) enable interrupt disable interrupt p0.2 (int) p0.1 (int) p0.0 (int) figure 9-3. port 0 interrupt control register (p0int)
s3c9228/p9228 i/o p orts 9- 5 port 0 interrupt pending bits (intpnd1.3-.0) d6h, page 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb intpnd1 bit configuration settings: 0 1 p0.3 (int) interrupt is pending (when read) no interrupt pending (when read), clear pending bit (when write) p0.2 (int) p0.1 (int) p0.0 (int) p1.3 (int) p1.2 (int) p1.1 (int) p1.0 (int) figure 9-4. port 0 interrupt pending bits (intpnd1.3-.0) port 0 interrupt edge selection register (p0edge) eeh, page 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p0edge bit configuration settings: 0 1 p0.3 (int) rising edge detection falling edge detection p0.2 (int) p0.1 (int) p0.0 (int) not used figure 9-5. port 0 interrupt edge selection register (p0edge) port 0 pull-up control register (p0pur) ech, page 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p0pur bit configuration settings: 0 1 enable pull-up resistor disable pull-up resistor not used p0.3 p0.2 p0.1 p0.0 figure 9-6. port 0 pull-up control register (p0pur)
i/o ports s3c9228/p 9228 9- 6 port 1 port 1 is an 4-bit i/o port with individually configurable pins. port 1 pins are accessed directly by writing or reading the port 1 data register, p1 at location e5h in page 0. p1.0-p1.3 can serve as inputs (with or without pull- up), as outputs (push-pull or open-drain) or you can be configured the following functions. ? low-nibble pins (p1.0-p1.3): ad0-ad3, int port 1 control register (p1con) port 1 has a 8-bit control register: p1con for p1.0-p1.3. a reset clears the p1con register to "00h", configuring pins to input mode. you use control register setting to select input or output mode (push-pull or open-drain) and enable the alternative functions. when programming this port, please remember that any alternative peripheral i/o function you configure using the port 1 control register must also be enabled in the associated peripheral module. port 1 pull-up resistor control register (p1pur) using the port 1 pull-up resistor control register, p1pur (f0h, page 0), you can configure pull-up resistors to individual port 1 pins. port 1 interrupt enable, pending, and edge selection registers (p1int, intpnd1.7-.4, p1edge) to process external interrupts at the port 1 pins, three additional control registers are provided: the port 1 interrupt enable register p1int (f1h, page 0), the port 1 interrupt pending bits intpnd1.7-.4 (d6h, page 0), and the port 1 interrupt edge selection register p1edge (f2h, page 0). the port 1 interrupt pending register bits lets you check for interrupt pending conditions and clear the pending condition when the interrupt service routine has been initiated. the application program detects interrupt requests by polling the intpnd1.7-.4 register at regular intervals. when the interrupt enable bit of any port 1 pin is "1", a rising or falling edge at that pin will generate an interrupt request. the corresponding intpnd1 bit is then automatically set to "1" and the irq level goes low to signal the cpu that an interrupt request is waiting. when the cpu acknowledges the interrupt request, application software must the clear the pending condition by writing a "0" to the corresponding intpnd1 bit. port 1 control register (p1con) efh, page 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p1.3/ad3 (int) p1con bit-pair pin configuration settings: 00 01 10 11 n-channel open-drain output mode alternative function (ad0,ad1, ad2, ad3) p1.2/ad2 (int) p1.1/ad1 (int) p1.0/ad0 (int) push-pull output mode schmitt trigger input mode figure 9-7. port 1 control register (p1con)
s3c9228/p9228 i/o p orts 9- 7 port 1 interrupt control register (p1int) f1h, page 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb not used p1int bit configuration settings: 0 1 p1.3 (int) enable interrupt disable interrupt p1.2 (int) p1.1 (int) p1.0 (int) figure 9-8. port 1 interrupt control register (p1int) port 1 interrupt pending bits (intpnd1.7-.4) d6h, page 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb intpnd1 bit configuration settings: 0 1 p0.3 (int) interrupt is pending (when read) no interrupt pending (when read), clear pending bit (when write) p0.2 (int) p0.1 (int) p0.0 (int) p1.3 (int) p1.2 (int) p1.1 (int) p1.0 (int) figure 9-9. port 1 interrupt pending bits (intpnd1.7-.4)
i/o ports s3c9228/p 9228 9- 8 port 1 interrupt edge selection register (p1edge) f2h, page 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p1edge bit configuration settings: 0 1 p1.3 (int) rising edge detection falling edge detection p1.2 (int) p1.1 (int) p1.0 (int) not used figure 9-10. port 1 interrupt edge selection register (p1edge) port 1 pull-up control register (p1pur) f0h, page 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p1pur bit configuration settings: 0 1 enable pull-up resistor disable pull-up resistor not used p1.3 p1.2 p1.1 p1.0 figure 9-11. port 1 pull-up control register (p1pur)
s3c9228/p9228 i/o p orts 9- 9 port 2 port 2 is an 4-bit i/o port with individually configurable pins. port 2 pins are accessed directly by writing or reading the port 2 data register, p2 at location e6h in page 0. p2.0-p2.3 can serve as inputs (with or without pull- up), as outputs (push-pull or open-drain) or you can be configured the following functions. ? low-nibble pins (p2.0-p2.3): sck, so, si, seg0-seg1 port 2 control register (p2con) port 2 has a 8-bit control register: p2con for p2.0-p2.3. a reset clears the p2con register to "00h", configuring pins to input mode. you use control register setting to select input or output mode (push-pull or open-drain) and enable the alternative functions. when programming this port, please remember that any alternative peripheral i/o function you configure using the port 2 control register must also be enabled in the associated peripheral module. port 2 pull-up resistor control register (p2pur) using the port 2 pull-up resistor control register, p2pur (f4h, page 0), you can configure pull-up resistors to individual port 2 pins. port 2 control register (p2con) f3h, page 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p2.3 p2con bit-pair pin configuration settings: 00 01 10 11 n-channel open-drain output mode alternative function (sck, so) p2.2/si p2.1/so/seg0 p2.0/sck/seg1 push-pull output mode schmitt trigger input mode (si,sck) figure 9-12. port 2 control register (p2con)
i/o ports s3c9228/p 9228 9- 10 port 2 pull-up control register (p2pur) f4h, page 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p2pur bit configuration settings: 0 1 enable pull-up resistor disable pull-up resistor not used p2.3 p2.2 p2.1 p2.0 figure 9-13. port 2 pull-up control register (p2pur)
s3c9228/p9228 i/o p orts 9- 11 port 3 port 3 is an 2-bit i/o port with individually configurable pins. port 3 pins are accessed directly by writing or reading the port 3 data register, p3 at location e7h in page 0. p3.0-p3.1 can serve as inputs (with or without pull- up, and high impedance input), as outputs (push-pull or open-drain) or you can be configured the following functions. ? low-nibble pins (p3.0-p3.1): seg2-seg3, intp port 3 control register (p3con) port 3 has a 8-bit control register: p3con for p3.0-p3.1. a reset clears the p3con register to "00h", configuring pins to input mode. you use control register setting to select input or output mode (push-pull or open-drain). port 3 pull-up resistor control register (p3pur) using the port 3 pull-up resistor control register, p3pur (f6h, page 0), you can configure pull-up resistors to individually port 3 pins. port 3 interrupt enable, pending, and edge selection registers(p3int, intpnd2.5-.4, p3edge) to process external interrupts at the port 3 pins, three additional control registers are provided: the port 3 interrupt enable register p3int (f7h, page 0), the port 3 interrupt pending bits intpnd2.5-.4 (d7h, page 0), and the port 3 interrupt edge selection register p3edge (f8h, page 0). the port 3 interrupt pending register bits lets you check for interrupt pending conditions and clear the pending condition when the interrupt service routine has been initiated. the application program detects interrupt requests by polling the intpnd2.5-.4 register at regular intervals. when the interrupt enable bit of any port 3 pin is "1", a rising or falling edge at that pin will generate an interrupt request. the corresponding intpnd2 bit is then automatically set to "1" and the irq level goes low to signal the cpu that an interrupt request is waiting. when the cpu acknowledges the interrupt request, application software must the clear the pending condition by writing a "0" to the corresponding intpnd2 bit. port 3 control register (p3con) f5h, page 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb not used p3.1/seg2 (intp) p3.0/seg3 (intp) p3con bit-pair pin configuration settings: 00 01 10 11 n-channel open-drain output mode not available push-pull output mode schmitt trigger input mode figure 9-14. port 3 control register (p3con)
i/o ports s3c9228/p 9228 9- 12 port 3 interrupt control register (p3int) f7h, page 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb not used p3int bit configuration settings: 0 1 enable interrupt disable interrupt p3.1 (intp) p3.0 (intp) figure 9-15. port 3 interrupt control register (p3int) port 3 interrupt pending bits (intpnd2.5-.4) d7h, page 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb intpnd2 bit configuration settings: 0 1 interrupt is pending (when read) no interrupt pending (when read), clear pending bit (when write) timer 1/a not used timer b sio watch timer p3.0 (intp) p3.0 (intp) figure 9-16. port 3 interrupt pending bits (intpnd2.5-.4)
s3c9228/p9228 i/o p orts 9- 13 port 3 interrupt edge selection register (p3edge) f8h, page 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p3edge bit configuration settings: 0 1 rising edge detection falling edge detection p3.1 (intp) p3.0 (intp) not used figure 9-17. port 3 interrupt edge selection register (p3edge) port 3 pull-up control register (p3pur) f6h, page 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p3pur bit configuration settings: 0 1 enable pull-up resistor disable pull-up resistor not used p3.1 p3.0 figure 9-18. port 3 pull-up control register (p3pur)
i/o ports s3c9228/p 9228 9- 14 port 4 port 4 is an 8-bit i/o port with individually configurable pins. port 4 pins are accessed directly by writing or reading the port 4 data register, p4 at location e8h in page 0. p4.0-p4.7 can serve as inputs or as push-pull, open-drain outputs. you can configure the following alternative functions with lcd port control register, lpot: ? low-nibble pins (p4.0-p4.3): seg4-seg7 ? high-nibble pins (p4.4-p4.7): seg8-seg11 port 4 control registers (p4conh, p4conl) port 4 has two 8-bit control registers: p4conh for p4.4-p4.7 and p4conl for p4.0-p4.3. a reset clears the p4conh and p4conl registers to "00h", configuring all pins to input mode. you use control registers setting to select input or output mode. port 4 control register, high byte (p4conh) f9h, page 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p4.5/seg9 p4.4/seg8 p4conh bit-pair pin configuration settings: 00 01 10 11 n-channel open-drain output mode input mode with pull-up push-pull output mode input mode p4.6/seg10 p4.7/seg11 figure 9-19. port 4 high-byte control register (p4conh) port 4 control register, low byte (p4conl) fah, page 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p4.1/seg5 p4.0/seg4 p4conl bit-pair pin configuration settings: 00 01 10 11 n-channel open-drain output mode input mode with pull-up push-pull output mode input mode p4.2/seg6 p4.3/seg7 figure 9-20. port 4 low-byte control register (p4conl)
s3c9228/p9228 i/o p orts 9- 15 port 5 port 5 is an 8-bit i/o port with individually configurable pins. port 5 pins are accessed directly by writing or reading the port 5 data register, p5 at location e9h in page 0. p5.0-p5.7 can serve as inputs or as push-pull, open-drain outputs. you can configure the following alternative functions with lcd port control register, lpot: ? low-nibble pins (p5.0-p5.3): seg12-seg15 ? high-nibble pins (p5.4-p5.7): seg16-seg19, com4-com7 port 5 control registers (p5conh, p5conl) port 5 has two 8-bit control registers: p5conh for p5.4-p5.7 and p4conl for p5.0-p5.3. a reset clears the p5conh and p5conl registers to "00h", configuring all pins to input mode. you use control registers setting to select input or output mode. port 5 control register, high byte (p5conh) fbh, page 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p5.5/seg17/com6 p5.4/seg16/com7 p5conh bit-pair pin configuration settings: 00 01 10 11 n-channel open-drain output mode input mode with pull-up push-pull output mode input mode p5.6/seg18/com5 p5.7/seg19/com4 figure 9-21. port 5 high-byte control register (p5conh) port 5 control register, low byte (p5conl) fch, page 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p5.1/seg13 p5.0/seg12 p5conl bit-pair pin configuration settings: 00 01 10 11 n-channel open-drain output mode input mode with pull-up push-pull output mode input mode p5.2/seg14 p5.3/seg15 figure 9-22. port 5 low-byte control register (p5conl)
i/o ports s3c9228/p 9228 9- 16 port 6 port 6 is an 4-bit i/o port with individually configurable pins. port 6 pins are accessed directly by writing or reading the port 6 data register, p6 at location eah in page 0. p6.0-p6.3 can serve as inputs or as push-pull, open-drain outputs. you can configure the following alternative functions with lcd port control register, lpot: ? low-nibble pins (p6.0-p6.3): com0-com3 port 6 control register (p6con) port 6 has a 8-bit control register: p6conh for p6.0-p6.3. a reset clears the p6con registers to "00h", configuring all pins to input mode. you use control registers setting to select input or output mode. port 6 control register, low byte (p6con) fdh, page 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p6.1/com2 p6.0/com3 p6con bit-pair pin configuration settings: 00 01 10 11 n-channel open-drain output mode input mode with pull-up push-pull output mode input mode p6.2/com1 p6.3/com0 figure 9-23. port 6 control register (p6con)
s3c9228/p9228 ( preliminary spec ) basic timer 10- 1 10 basic timer overview basic timer (bt) can be used in two different ways: ? as a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction. ? to signal the end of the required oscillation stabilization interval after a reset or a stop mode release. the functional components of the basic timer block are: ? clock frequency divider ( f xx divided by 4096, 1024, 128, or 16) with multiplexer ? 8-bit basic timer counter, btcnt (ddh, read-only) ? basic timer control register, btcon (dch, read/write)
basic timer s3c9228 /p9228 ( preliminary spec ) 10- 2 basic timer control register (btcon) the basic timer control register, btcon, is used to select the input clock frequency, to clear the basic timer counter and frequency dividers, and to enable or disable the watchdog timer function. it is located in page 0, address dch, and is read/write addressable using register addressing mode. a reset clears btcon to "00h". this enables the watchdog function and selects a basic timer clock frequency of f xx /4096. to disable the watchdog function, you must write the signature code ?1010b? to the basic timer register control bits btcon.7?btcon.4. the 8-bit basic timer counter, btcnt (page 0, ddh), can be cleared at any time during normal operation by writing a "1" to btcon.1. to clear the frequency dividers for the basic timer input clock and timer counters, you write a "1" to btcon.0. basic timer control register (btcon) dch, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb divider clear bit for basic timer and timer counters: 0 = no effect 1 = clear divider basic timer counter clear bit: 0 = no effect 1 = clear btcnt basic timer input clock selection bits: 00 = f xx /4096 01 = f xx /1024 10 = f xx /128 11 = f xx /16 watchdog function enable bits: 1010b other value = disable watchdog timer = enable watchdog timer figure 10-1. basic timer control register (btcon)
s3c9228/p9228 ( preliminary spec ) basic timer 10- 3 basic timer function description watchdog timer function you can program the basic timer overflow signal (btovf) to generate a reset by setting btcon.7?btcon.4 to any value other than ?1010b?. (the ?1010b? value disables the watchdog function.) a reset clears btcon to ?00h?, automatically enabling the watchdog timer function. a reset also selects the cpu clock (as determined by the current clkcon register setting), divided by 4096, as the bt clock. a reset whenever a basic timer counter overflow occurs. during normal operation, the application program must prevent the overflow, and the accompanying reset operation, from occurring. to do this, the btcnt value must be cleared (by writing a "1" to btcon.1) at regular intervals. if a system malfunction occurs due to circuit noise or some other error condition, the bt counter clear operation will not be executed and a basic timer overflow will occur, initiating a reset. in other words, during normal operation, the basic timer overflow loop (a bit 7 overflow of the 8-bit basic timer counter, btcnt) is always broken by a btcnt clear instruction. if a malfunction does occur, a reset is triggered automatically. oscillation stabilization interval timer function you can also use the basic timer to program a specific oscillation stabilization interval following a reset or when stop mode has been released by an external interrupt. in stop mode, whenever a reset or an internal and an external interrupt occurs, the oscillator starts. the btcnt value then starts increasing at the rate of fxx/4096 (for reset), or at the rate of the preset clock source (for an internal and an external interrupt). when btcnt.3 overflows, a signal is generated to indicate that the stabilization interval has elapsed and to gate the clock signal off to the cpu so that it can resume normal operation. in summary, the following events occur when stop mode is released: 1. during stop mode, a power-on reset or an internal and an external interrupt occurs to trigger the stop mode release and oscillation starts. 2. if a power-on reset occurred, the basic timer counter will increase at the rate of fx x /4096. if an internal and an external interrupt is used to release stop mode, the btcnt value increases at the rate of the preset clock source. 3. clock oscillation stabilization interval begins and continues until bit 3 of the basic timer coun ter overflows. 4. when a btcnt.3 overflow occurs, normal cpu operation resumes.
basic timer s3c9228 /p9228 ( preliminary spec ) 10- 4 note: during a power-on reset operation, the cpu is idle during the required oscillation stabilization interval (until bit 4 of the basic timer counter overflows). mux f xx /4096 div f xx /1024 f xx /128 f xx /16 f xx bits 3, 2 bit 0 basic timer control register (write '1010xxxxb' to disable) clear bit 1 reset or stop data bus 8-bit up counter (btcnt, read-only) start the cpu (note) ovf reset r figure 10-2. basic timer block diagram
s3c9228/p9228 timer 1 11- 1 11 timer 1 one 16-bit timer mode (timer 1) the 16-bit timer 1 is used in one 16-bit timer or two 8-bit timers mode. if tacon.7 is set to "1", timer 1 is used as a 16-bit timer. if tacon.7 is set to "0", timer 1 is used as two 8-bit timers. ? one 16-bit tim er mode (timer 1) ? two 8-bit timers mode (timer a and b) overview the 16-bit timer 1 is an 16-bit general-purpose timer. timer 1 has the interval timer mode by using the appropriate tacon setting. timer 1 has the following functional components: ? clock frequency divider ( fxx divided by 512, 256, 64, 8, or 1, fxt, and t1clk: external clock) with multiplexer ? 16-bit counter (tacnt, tbcnt), 16-bit comparator, and 16-bit reference data register (tadata, tbdata) ? timer 1 match interrupt generation ? timer 1 control register, tacon (page 0, bbh, read/write) function description interval timer function the timer 1 module can generate an interrupt: the timer 1 match interrupt (t1int). the t1int pending condition should be cleared by software when it has been serviced. even though t1int is disabled, the application's service routine can detect a pending condition of t1int by the software and execute it's sub-routine. when this case is used, the t1int pending bit must be cleared by the application sub-routine by writing a "0" to the intpnd2.0 pending bit. in interval timer mode, a match signal is generated when the counter value is identical to the values written to the timer 1 reference data registers, tadata and tbdata. the match signal generates a timer 1 match interrupt and clears the counter. if, for example, you write the value 32h and 10h to tadata and tbdata, respectively, and 8eh to tacon, the counter will increment until it reaches 3210h. at this point, the timer 1 interrupt request is generated, the counter value is reset, and counting resumes.
timer 1 s3c9228/p922 8 11- 2 timer 1 control register (tacon) you use the timer 1 control register, tacon, to ? enable the timer 1 operating (interval timer) ? select the timer 1 input clock frequency ? clear the timer 1 counter, tacnt and tbcnt ? enable the timer 1 interrupt tacon is located in page 0, at address bbh, and is read/write addressable using register addressing mode. a reset clears tacon to "00h". this sets timer 1 to disable interval timer mode, selects an input clock frequency of fxx/512, and disables timer 1 interrupt. you can clear the timer 1 counter at any time during normal operation by writing a "1" to tacon.3. to enable the timer 1 interrupt, you must write tacon.7, tacon.2, and tacon.1 to "1". to generate the exact time interval, you should write tacon.3 and intpnd2.0, which cleared counter and interrupt pending bit. to detect an interrupt pending condition when t1int is disabled, the application program polls pending bit, intpnd.2.0. when a "1" is detected, a timer 1 interrupt is pending. when the t1int sub- routine has been serviced, the pending condition must be cleared by software by writing a "0" to the timer 1 interrupt pending bit, intpnd2.0. timer a control register (tacon) bbh, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb timer 1/a interrupt enable bit: 0 = disable interrupt 1 = enable interrupt not used timer 1/a counter enable bit: 0 = disable counting operation 1 = enable counting operation timer 1/a counter clear bit: 0 = no affect 1 = clear the timer 1/a counter (when write) one 16-bit timer or two 8-bit timers mode: 0 = two 8-bit timers mode (timer a/b) 1 = one 16-bit timer mode (timer 1) timer 1/a clock selection bits: 000 = fxx/512 001 = fxx/256 010 = fxx/64 011 = fxx/8 100 = fxx 101 = fxt (sub clock) 110 = t1clk (external clock) 111 = not available figure 11-1. timer 1 control register (tacon)
s3c9228/p9228 timer 1 11- 3 note: when one 16-bit timer mode (tacon.7 <- "1": timer 1) tacon.6-.4 m u x 1/8 1 /64 1 /256 1 /512 intpnd2.0 taout t1int 1/1 div r fxt t1clk (x in or xt in ) fxx btcon.0 tacon.2 tbcnt tacnt 16-bit comparator tbdata buffer tadata buffer tbdata tadata lsb msb lsb msb match signal counter clear signal tacon.1 match r tacon.3 data bus data bus clear figure 11-2. timer 1 block diagram (one 16-bit mode)
timer 1 s3c9228/p922 8 11- 4 two 8-bit timers mode (timer a and b) overview the 8-bit timer a and b are the 8-bit general-purpose timers. timer a and b have the interval timer mode by using the appropriate tacon and tbcon setting, respectively. timer a and b have the following functional components: ? clock frequency divider with multiplexer ? fxx divided by 512, 256, 64, 8 or 1, fxt, and t1clk (external clock) for timer a ? fxx divided by 512, 256, 64, 8 or 1, and fxt for timer b ? 8-bit counter (tacnt, tbcnt), 8-bit comparator, and 8-bit reference data register (tadata, tbdata) ? timer a have i/o pin for match output (taout) ? timer a match interrupt generation ? timer a control register, tacon (pag e 0, bbh, read/write) ? timer b match interrupt generation ? timer b control register, tbcon (page 0, bah, read/write) timer a and b control register (tacon, tbcon) you use the timer a and b control register, tacon and tbcon, to ? enable the timer a (interval timer mode) and b operating (interval timer mode) ? select the timer a and b input clock frequency ? clear the timer a and b counter, tacnt and tbcnt ? enable the timer a and b interrupt
s3c9228/p9228 timer 1 11- 5 tacon and tbcon are located in page 0, at address bbh and bah, and is read/write addressable using register addressing mode. a reset clears tacon to "00h". this sets timer a to disable interval timer mode, selects an input clock frequency of fxx/512, and disables timer a interrupt. you can clear the timer a counter at any time during normal operation by writing a "1" to tacon.3. a reset clears tbcon to "00h". this sets timer b to disable interval timer mode, selects an input clock frequency of fxx/512, and disables timer a interrupt. you can clear the timer b counter at any time during normal operation by writing a "1" to tbcon.3. to enable the timer a interrupt (taint) and timer b interrupt (tbint), you must write tacon.7 to "0", tacon.2 (tbcon.2) and tacon.1 (tbcon.1) to "1". to generate the exact time interval, you should write tacon.3 (tbcon.3) and intpnd2.0 (intpnd2.1), which cleared counter and interrupt pending bit. to detect an interrupt pending condition when taint and tbint is disabled, the application program polls pending bit, intpnd2.0 and intpnd2.1. when a "1" is detected, a timer a interrupt (taint) and timer b interrupt (tbint) is pending. when the taint and tbint sub-routine has been serviced, the pending condition must be cleared by software by writing a "0" to the timer a and b interrupt pending bit, intpnd2.0 and intpnd2.1. timer a control register (tacon) e4h, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb timer a interrupt enable bit: 0 = disable interrupt 1 = enable interrupt not used timer a counter enable bit: 0 = disable counting operation 1 = enable counting operation timer a counter clear bit: 0 = no affect 1 = clear the timer a counter (when write) one 16-bit timer or two 8-bit timers mode: 0 = two 8-bit timers mode (timer a/b) 1 = one 16-bit timer mode (timer 1) timer a clock selection bits: 000 = fxx/512 001 = fxx/256 010 = fxx/64 011 = fxx/8 100 = fxx 101 = fxt (sub clock) 110 = t1clk (external clock) 111 = not available figure 11-3. timer a control register (tacon)
timer 1 s3c9228/p922 8 11- 6 timer b control register (tbcon) bah, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb timer b match interrupt enable bit: 0 = disable match interrupt 1 = enable match interrupt not used timer b count enable bit: 0 = disable counting operating 1 = enable counting operating timer b counter clear bit: 0 = no effect 1 = clear the timer b counter (when write) timer b clock selection bits: 000 = f x x/512 001 = f x x/256 010 = f x x/64 011 = fxx/8 100 = fxx (system clock) 101 = fxt (sub clock) 110 = not available 111 = not available not used figure 11-4. timer b control register (tbcon)
s3c9228/p9228 timer 1 11- 7 function description interval timer function (timer a and timer b) the timer a and b module can generate an interrupt: the timer a match interrupt (taint) and the timer b match interrupt (tbint). the timer a match interrupt pending condition (intpnd2.0) and the timer b match interrupt pending condition (intpnd2.1) must be cleared by software in the application's interrupt service by means of writing a "0" to the intpnd2.0 and intpnd2.1 interrupt pending bit. even though taint and tbint are disabled, the application's service routine can detect a pending condition of taint and tbint by the software and execute it's sub-routine. when this case is used, the taint and tbint pending bit must be cleared by the application sub-routine by writing a "0" to the corresponding pending bit intpnd2.0 and intpnd2.1. in interval timer mode, a match signal is generated when the counter value is identical to the values written to the timer a or timer b reference data registers, tadata or tbdata. the match signal generates corresponding match interrupt and clears the counter. if, for example, you write the value 20h to tadata and 0eh to tacon, the counter will increment until it reaches 20h. at this point, the timer a interrupt request is generated, the counter value is cleared, and counting resumes and you write the value 10h to tbdata, "0" to tacon.7, and 0eh to tbcon, the counter will increment until it reaches 10h. at this point, tb interrupt request is generated, the counter value is cleared and counting resumes.
timer 1 s3c9228/p922 8 11- 8 note: when two 8-bit timers mode (tacon.7 <- "0": timer a) tacon.6-.4 m u x 1/8 1 /64 1 /256 1 /512 intpnd2.0 taout taint div r fxt t1clk/ p0.1 (x in or xt in ) fxx btcon.0 tacon.2 8-bit comparator tadata buffer tadata register lsb msb lsb msb match signal counter clear signal tacon.1 match r tacon.3 data bus data bus tacnt (8-bit up-counter) clear 1/1 figure 11-5. timer a block diagram(two 8-bit timers mode)
s3c9228/p9228 timer 1 11- 9 1/1 1/8 1 /64 1 /256 1 /512 note: when two 8-bit timers mode (tacon.7 <- "0": timer b) tbcon.6-.4 m u x intpnd2.1 tbint div r fxt (x in or xt in ) fxx btcon.0 tbcon.2 8-bit comparator tbdata buffer tbdata register lsb msb lsb msb match signal counter clear signal tbcon.1 match r tbcon.3 data bus data bus tbcnt (8-bit up-counter) clear figure 11-6. timer b block diagram (two 8-bit timers mode)
timer 1 s3c9228/p922 8 11- 10 notes
s3c9228/p9228 watch timer 12- 1 12 watch timer overview watch timer functions include real-time and watch-time measurement and interval timing for the system clock. to start watch timer operation, set bit 1 of the watch timer control register, wtcon.1 to "1". and if you want to service watch timer overflow interrupt, then set the wtcon.6 to ?1?. the watch timer overflow interrupt pending condition (intpnd2.3) must be cleared by software in the application's interrupt service routine by means of writing a "0" to the intpnd2.3 interrupt pending bit. after the watch timer starts and elapses a time, the watch timer interrupt pending bit (intpnd2.3) is automatically set to "1", and interrupt requests commence in 3.91ms, 0.25, 0.5 and 1-second intervals by setting watch timer speed selection bits (wtcon.3 ? .2). the watch timer can generate a steady 0.5 khz, 1 khz, 2 khz, or 4 khz signal to buz output pin for buzzer. by setting wtcon.3 and wtcon.2 to "11b", the watch timer will function in high-speed mode, generating an interrupt every 3.91 ms. high-speed mode is useful for timing events for program debugging sequences. also, you can select watch timer clock source by setting the wtcon.7 appropriately value. the watch timer supplies the clock frequency for the lcd controller (f lcd ). therefore, if the watch timer is disabled, the lcd controller does not operate. watch timer has the following functional components: ? real time and watch-time measurement ? using a main or sub clock source (main clock divided by 2 7 (fx/128) or sub clock( fxt)) ? clock source generation for lcd controller (f lcd ) ? i/o pin for buzzer output frequency generator (p0.3, buz) ? timing tests in high-speed mode ? watch timer overflow interrupt generation ? watch timer control regi ster, wtcon (page 0, dah, read/write)
watch timer s3c922 8/p9228 12- 2 watch timer control register (wtcon) the watch timer control register, wtcon is used to select the input clock source, the watch timer interrupt time and buzzer signal, to enable or disable the watch timer function. it is located in page 0 at address dah, and is read/write addressable using register addressing mode. a reset clears wtcon to "00h". this disable the watch timer and select fx/128 as the watch timer clock. so, if you want to use the watch timer, you must write appropriate value to wtcon. buzzer signal selection bits: 00 = 0.5 khz 01 = 1 khz 10 = 2 khz 11 = 4 khz watch timer control register (wtcon) dah, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb watch timer enable/disable bit: 0 = disable watch timer; clear frequency dividing circuits 1 = enable watch timer not used watch timer speed selection bits: 00 = set watch timer interrupt to 1 s 01 = set watch timer interrupt to 0.5 s 10 = set watch timer interrupt to 0.25 s 11 = set watch timer interrupt to 3.91 ms watch timer clock selection bit: 0 = main clock divided by 2 7 (fx/128) 1 = sub clock (fxt) watch timer int enable/disable bit: 0 = disable watch timer int 1 = enable watch timer int figure 12-1. watch timer control register (wtcon)
s3c9228/p9228 watch timer 12- 3 watch timer circuit diagram wt int enable wtcon.1 wtcon.2 wtcon.3 wtcon.4 wtcon.5 wtcon.6 enable/disable selector circuit mux intpnd2.3 wtint wtcon.6 f w /2 15 f w /2 14 f w /2 13 f w /2 7 f w /64 (0.5 khz) f w /32 (1 khz) f w /16 (2 khz) f w /8 (4 khz) (1 hz) f x = main clock (where fx = 4.19 mhz) fxt = sub clock (32,768 hz) f w = watch timer frequency clock selector frequency dividing circuit f w 32.768 khz f xt f lcd = 2048 hz wtcon.7 wtcon.0 8 buz (p0.3) fx/128 figure 12-2. watch timer circuit diagram
watch timer s3c922 8/p9228 12- 4 notes
s3c9228/p9228 lcd controller/driv er 13- 1 1 3 lcd controller/driv er overview the s3c9228/p9228 microcontroller can directly drive an up-to- 128 -dot ( 16 segments x 8 commons) lcd panel. its lcd block has the following components: ? lcd control ler/driver ? display ram for storing display data ? 16 segment output pins (seg0 ? seg 15 ) ? 8 common output pins (com0? com7 ) ? internal resistor circuit for lcd bias to use the lcd controller, bit 2 in the watch mode register wmod must be set to 1 because lcdck is supplied by the watch timer. the lcd mode control register, l mod , is used to turn the lcd display on or off, to s elect lcd clock frequency, to turn the com signal output on or off, to select bias and duty, and to switch the port 3 high impedance or normal i/o port . data written to the lcd display ram can be transferred to the segment signal pins automatically without program control. the lcd port control register, lpot, is used to determine the lcd signal pins used for display output. when a sub clock is selected as the lcd clock source, the lcd display is enabled even during main clock stop and idle modes. lcd controller/ driver com0-com3 seg0/p2.1- seg15/p5.3 16 4 8 data bus com4/seg19- com7/seg16 4 figure 13- 1. lcd function diagram
lcd controller/driver s3c9228/p9228 13- 2 lcd circuit diagram seg15/p5.3 com4/seg19/p5.7 com7/seg16/p5.4 160 16 data bus port latch lpot display ram (page1) port latch port latch timing controller mux seg control or selector com control or selector f lcd seg0/p2.1 com3/p6.0 com0/p6.3 com control lcd voltage control port 3 control p3.1/intp/seg2 p3.0/intp/seg3 lmod 16 4 8 2 figure 13- 2. lcd circuit diagram
s3c9228/p9228 lcd controller/driv er 13- 3 lcd ram address area ram addresses of page 1 are used as lcd data memory. when the bit value of a display segment is "1", the lcd display is turned on; when the bit value is "0", the display is turned off. display ram data are sent out through segment pins seg0?seg 19 using a direct memory access (dma) method that is synchronized with the f lcd signal. ram addresses in this location that are not used for lcd display can be allocated to general-purpose use. com0 com1 com2 com3 b0 b1 b2 b3 b4 b5 b6 b7 seg0 com7 com6 com5 com4 seg1 seg2 seg3 100h 101h 102h 103h 111h 112h 113h seg17 seg18 seg19 figure 13- 3. lcd display data ram organization table 13- 1. common and segment pins per duty cycle duty common pins segment pins dot number 1/ 8 com0?com 7 16 pins 128 dots 1/4 com0? com3 20 pins 80 dots 1/3 com0?com 2 20 pins 60 dots
lcd controller/driver s3c9228/p9228 13- 4 lcd mode control register (lmod) a lmod is located in page 0, at address feh, and is read/write addressable using register addressing mode. it has the following control functions. ? lcd duty and bias selection ? lcd clock selection ? lcd display control ? coms signal output control ? p3 high impedance control the lmod register is used to turn the lcd display on/off, to select duty and bias, to select lcd clock, to control port 3 high impedance/normal i/o port, and to turn the com signal output on/off. following a reset , all lmod values are cleared to "0". this turns off the lcd display, select 1/3 duty and 1/3 bias, and select 256hz for lcd clock. the lcd clock signal determines the frequency of com signal scanning of each segment output. this is also referred as the lcd frame frequency. since the lcd clock is generated by watch timer clock ( fw). the watch timer should be enabled when the lcd display is turned on. lcd mode control register (lmod) feh, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb not used lcd duty and bias selection bits: 00 = 1/3 duty, 1/3 bias (com0-com2, seg0-seg19) 01 = 1/4 duty, 1/3 bias (com0-com3, seg0-seg19) 10 = 1/8 duty, 1/4 bias (com0-com7, seg0-seg15) 11 = 1/8 duty, 1/5 bias (com0-com7, seg0-seg15) com pins high impedance control bit: 0 = normal coms signal output 1 = high impendane com pins lcd clock selection bits: 00 = fw/2 7 (256 hz when fw is 32.768 khz) 01 = fw/2 6 (512 hz when fw is 32.768 khz) 10 = fw/2 5 (1024 hz when fw is 32.768 khz) 11 = fw/2 4 (2048 hz when fw is 32.768 khz) port 3 high impendance control bit 0 = normal i/o 1 = high impendane input lcd display control bit 0 = display off 1 = normal display on figure 13-4. lcd mode control register (lmod)
s3c9228/p9228 lcd controller/driv er 13- 5 lcd port control register the lcd port control register lpot is used to control lcd signal pins or normal i/o pins. following a reset , a lpot values are cleared to "0". lcd port control register d8h, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb not used seg0/p2.1 selection bit: 0 = seg port 1 = normal i/o port seg4-seg19 and com0-com3 selection bits: 000 = p4.0-p6.3: lcd signal pins 001 = p4.0-p4.3: normal i/o, p4.4-p6.3: lcd signal pins 010 = p4.0-p4.7: normal i/o, p5.0-p6.3: lcd signal pins 011 = p4.0-p5.3: normal i/o, p5.4-p6.3: lcd signal pins 100 = p4.0-p5.7: normal i/o, p6.0-p6.3: lcd signal pins 101 = p4.0-p6.3: normal i/o 110 = not available 111 = not available seg1/p2.0 selection bit: 0 = seg port 1 = normal i/o port seg2/p3.1 selection bit: 0 = seg port 1 = normal i/o port seg3/p3.0 selection bit: 0 = seg port 1 = normal i/o port figure 13-5. lcd port control register
lcd controller/driver s3c9228/p9228 13- 6 lcd voltage dividing resistors 1/5 bias s3c9228/p9228 v dd r r r r r lmod.4 v lc1 v lc2 v lc3 v lc4 v lc5 v ss 1/4 bias s3c9228/p9228 v dd r r r r r lmod.4 v lc1 v lc2 v lc3 v lc4 v lc5 v ss 1/3 bias s3c9228/p9228 v dd r r r r r lmod.4 v lc1 v lc2 v lc3 v lc4 v lc5 v ss figure 13-6. internal voltage dividing resistor connection common (com) signals the common signal output pin selection (com pin selection) varies according to the selected duty cycle. ? in 1/3 duty mode, com0-com2 pins are selected ? in 1/4 duty mode, com0-com3 pins are selected ? in 1/8 duty mode, com0-com7 pins are selected segment (seg) signals the 19 lcd segment signal pins are connected to corresponding display ram locations at page 1. bits of the display ram are synchronized with the common signal output pins. when the bit value of a display ram location is "1", a select signal is sent to the corresponding segment pin. when the display bit is "0", a 'no-select' signal to the corresponding segment pin.
s3c9228/p9228 lcd controller/driv er 13- 7 1 frame fr v dd v ss com0 com1 com2 com3 com4 com5 com6 com7 com1 v lc2 (v lc3 ) v lc4 v ss v dd v lc1 seg0 v lc2 (v lc3 ) v lc4 v ss v dd v lc1 com2 v lc2 (v lc3 ) v lc4 v ss v dd v lc1 com0 v lc2 ( v lc3 ) v lc4 v ss v dd v lc1 seg0-com0 + v dd 0v + 1/4v lcd -v lcd - 1/4v lcd 0 1 2 3 7 4 6 5 0 1 2 3 7 4 6 5 s e g 0 s e g 1 s e g 2 s e g 3 s e g 4 figure 13-7 . lcd signal waveforms (1/ 8 duty, 1/ 4 bias)
lcd controller/driver s3c9228/p9228 13- 8 1 frame v dd v ss 0 1 2 3 0 1 2 3 com1 v ss v dd v lc1 ( v lc2 ) v lc3 ( v lc4 ) com2 v ss v dd v lc1 ( v lc2 ) v lc3 ( v lc4 ) com3 v ss v dd v lc1 ( v lc2 ) v lc3 ( v lc4 ) seg0 v ss v dd v lc1 ( v lc2 ) v lc3 ( v lc4 ) seg1 v ss v dd v lc1 ( v lc2 ) v lc3 ( v lc4 ) com0-seg0 + v lcd com0 v ss v dd v lc1 ( v lc2 ) v lc3 ( v lc4 ) + 1/3 v lcd 0v - 1/3 v lcd - v lcd com0 com1 com2 com3 seg1 seg0 figure 13-8. lcd signal waveforms (1/4 duty, 1/ 3 bias)
s3c9228/p9228 lcd controller/driv er 13- 9 1 frame v dd v ss 0 1 2 com1 v ss v dd v lc1 ( v lc2 ) v lc3 ( v lc4 ) com2 v ss v dd v lc1 ( v lc2 ) v lc3 ( v lc4 ) seg0 v ss v dd v lc1 ( v lc2 ) v lc3 ( v lc4 ) seg1 v ss v dd v lc1 ( v lc2 ) v lc3 ( v lc4 ) com0-seg0 + v lcd com0 v ss v dd v lc1 ( v lc2 ) v lc3 ( v lc4 ) + 1/3 v lcd 0v - 1/3 v lcd - v lcd com0 com1 com2 seg2 seg1 seg0 0 1 2 figure 13-9 . lcd signal waveforms (1/ 3 duty, 1/ 3 bias)
lcd controller/driver s3c9228/p9228 13- 10 notes
s3c9228/p9228 a/d c onverter 14- 1 14 10-bit analog-to-digital converter overview the 10-bit a/d converter (adc) module uses successive approximation logic to convert analog levels entering at one of the four input channels to equivalent 10 -bit digital values. the an alog input level must lie between the av ref and av ss values. the a/d converter has the following components: ? analog comparator with successive approximation logic ? d/a converter logic (resistor string type) ? adc control register (adcon) ? four multiplexed analog data input pins (ad0?ad3) ? 10-bit a/d conversion data output register (addatah/addatal) ? 4 -bit digital input port (alternately, i/o port) function description to initiate an analog-to-digital conversion procedure, at first you must set with alternative function for adc input enable at port 1, the pin set with alternative function can be used for adc analog input. and you write the channel selection data in the a/d converter control register adcon.4?.5 to select one of the four analog input pins (ad0?3) and set the conversion start or enable bit, adcon.0. the read-write adcon register is located in page 0, at address d0h. the pins which are not used for adc can be used for normal i/o. during a normal conversion, adc logic initially sets the successive approximation register to 800h (the approximate half-way point of an 10 -bit register). this register is then updated automatically during each conversion step. the successive approximation block performs 10-bit conversions for one input channel at a time. you can dynamically select different channels by manipulating the channel selection bit value (adcon.5? 4) in the adcon register. to start the a/d conversion, you should set the enable bit, adcon.0. when a conversion is completed, adcon.3, the end-of-conversion(eoc) bit is automatically set to 1 and the result is dumped into the addatah/addatal register where it can be read. the a/d converter then enters an idle state. remember to read the contents of addatah/addatal before another conversion starts. otherwise, the previous result will be overwritten by the next conversion result. note because the a/d converter has no sample-and-hold circuitry, it is very important that fluctuation in the analog level at the ad0?ad3 input pins during a conversion procedure be kept to an absolute minimum. any change in the input level, perhaps due to noise, will invalidate the result. if the chip enters to stop or idle mode in conversion process, there will be a leakage current path in a/d block. you must use stop or idle mode after adc operation is finished.
a/d converter s3c9 228/p9228 14- 2 conversion timing the a/d conversion process requires 4 steps (4 clock edges) to convert each bit and 10 clocks to set-up a/d conversion. therefore, total of 50 clocks are required to complete an 10-bit conversion: when fxx/8 is selected for conversion clock with an 4.5 mhz fxx clock frequency, one clock cycle is 1.78 us. each bit conversion requires 4 clocks, the conversion rate is calculated as follows: 4 clocks/bit 10-bit + set-up time = 50 clocks, 50 clock 1.78 us = 89 us at 0.56 mhz (4.5 mhz/8) note that a/d converter needs at least 25 m s for conversion time. a/d converter control register (adcon) the a/d converter control register, adcon, is located at address d0h in page 0. it has three functions: ? analog input pin selection (bits 4 and 5) ? end-of-conversion status detection (bit 3) ? adc clock selection (bits 2 and 1) ? a/d operation start or enable (bit 0 ) after a reset, the start bit is turned off. you can select only one analog input channel at a time. other analog input pins (ad0?ad3) can be selected dynamically by manipulating the adcon.4?5 bits. and the pins not used for analog input can be used for normal i/o function. start or enable bit 0 = disable operation 1 = start operation (automatically disable the operation after conversion completes.) a/d converter control register (adcon) d0h, page0, r/w (eoc bit is read-only) .7 .6 .5 .4 .3 .2 .1 .0 msb lsb end-of-conversion bit 0 = not complete conversion 1 = complete conversion always logic zero a/d input pin selection bits: 00 = ad0 01 = ad1 10 = ad2 11 = ad3 clock selection bits: 00 = fxx/16 01 = fxx/8 10 = fxx/4 11 = fxx/1 figure 14-1. a/d converter control register (adcon)
s3c9228/p9228 a/d c onverter 14- 3 conversion data register addatah/addatal d1h/d2h, page 0, read only .9 .8 .7 .6 .5 .4 .3 .2 msb lsb (addatah) - - - - - - .1 .0 msb lsb (addatal) figure 14-2. a/d converter data register (addatah/addatal) internal reference voltage levels in the adc function block, the analog input voltage level is compared to the reference voltage. the analog input level must remain within the range v ss to v dd . different reference voltage levels are generated internally along the resistor tree during the analog conversion process for each conversion step. the reference voltage level for the first conversion bit is always 1/2 v dd . block diagram input pins ad0-ad3 (p1.0-p1.3) clock selector conversion result (addatah/addatal, d1h/d2h, page 0) - + to adcon.3 (eoc flag) successive approximation logic & register v dd v ss analog comparator 10-bit d/a converter m u x adcon.4-5 (select one input pin of the assigned pins) p1con (assign pins to adc input) adcon.0 (ad/c enable) adcon.0 (ad/c enable) . . . adcon.2-.1 figure 14-3. a/d converter functional block diagram
a/d converter s3c9 228/p9228 14- 4 s3c9228 ad0-ad3 analog input pin v dd 101 c (v ss adc input v dd ) figure 14-4. recommended a/d converter circuit for highest absolute accuracy
s3c9228/p9228 serial i/o interface 1 5- 1 1 5 serial i/o interfac e overview serial i/o modules, sio can interface with various types of external device that require serial data transfer. the components of sio function block are: ? 8-bit control register (s iocon ) ? clock selector logic ? 8-bit data buffer (siodata) ? 8-bit prescaler (siops) ? 3-bit serial clock counter ? serial data i/o pins (si, so) ? serial clock input/output pin (sck) the sio module can transmit or receive 8-bit serial data at a frequency determined by its corresponding control register settings. to ensure flexible data transmission rates, you can select an internal or external clock source. programming procedure to program the sio module, follow these basic steps: 1. configure the i/o pins at port (sck/si/so) by loading the appropriate value to the p2con register if necessary. 2. load an 8-bit value to the siocon control register to properly configure the serial i/o module. in this operation, siocon.2 must be set to "1" to enable the data shifter. 3. for interrupt generation, set the serial i/o interrupt enable bit (siocon) to "1". 4. when you transmit data to the serial buffer, write data to siodata and set siocon.3 to 1, the shift operation starts. 5. when the shift operation (transmit/receive) is completed, the sio pending bit (intpnd2.2) are set to "1" and sio interrupt request is generated.
serial i/o interface s3c9228/p9228 15- 2 sio control registers (siocon) the control register for serial i/o interface module, siocon, is located at e1h in page 0. it has the control setting for sio module. ? clock source selection (internal or external) for shift clock ? interrupt enable ? edge selection for shift operation ? clear 3-bit counter and start shift operation ? shift operation (transmit) enable ? mode selection (transmit/receive or receive-only) ? data direction selection (msb first or lsb first) a reset clears the siocon value to "00h". this configures the corresponding module with an internal clock source at the sck, selects receive-only operating mode, and clears the 3-bit counter. the data shift operation and the interrupt are disabled. the selected data direction is msb-first. serial i/o module control register (siocon) e1h, page 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb sio interrupt enable bit: 0 = disable sio interrupt 1 = enable sio interrupt not used sio shift operation enable bit: 0 = disable shifter and clock counter 1 = enable shifter and clock counter shift clock edge selection bit: 0 = t x at falling edeges, rx at rising edges. 1 = t x at rising edeges, rx at falling edges. data direction control bit: 0 = msb-first mode 1 = lsb-first mode sio mode selection bit: 0 = receive only mode 1 = transmit/receive mode sio counter clear and shift start bit: 0 = no action 1 = clear 3-bit counter and start shifting sio shift clock selection bit: 0 = internal clock (p.s clock) 1 = external clock (sck) figure 15- 1. serial i/o module control register (siocon)
s3c9228/p9228 serial i/o interface 1 5- 3 sio pre-scaler register (siops) the prescaler register for serial i/o interface module, siops, are located at e3h in page 0. the value stored in the sio pre-scale register, siops, lets you determine the sio clock rate (baud rate) as follows: baud rate = input clock (fxx/4)/( prescaler value + 1), or sck input clock. sio pre-scaler register (siops) e3h, page 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb baud rate = (f xx /4)/(siops + 1) figure 15-2. sio prescaler register (siops) sio block diagram sio int pending 3-bit counter clear intpnd2.2 fxx /2 siops (e3h, page 0) sck siocon.7 siocon.1 (interrupt enable) clk si siocon.3 data bus so m u x 1/2 8-bit p.s. 8 8-bit sio shift buffer (siodata, e2h, page 0) clk siocon.4 (edge select) siocon.5 (mode select) siocon.2 (shift enable) siocon.6 (lsb/msb first mode select) figure 15-3. sio functional block diagram
serial i/o interface s3c9228/p9228 15- 4 serial i/o timing diagram (sio) so transmit complete sio int set siocon.3 do7 do6 do5 do4 do3 do2 do1 do0 di7 di6 di5 di4 di3 di2 di1 di0 si sck figure 15-4 . serial i/o timing in transmit/receive mode ( tx at falling, siocon.4 = 0) sio int do7 do6 do5 do4 do3 do2 do1 do0 di7 di6 di5 di4 di3 di2 di1 di0 sck transmit complete si so set siocon.3 figure 15-5 . serial i/o timing in transmit/receive mode ( tx at rising, siocon.4 = 1)
s3c9228/p9228 elect rical data 16- 1 16 electrical data overview in this chapter, s3c9228/p9228 electrical characteristics are presented in tables and graphs. the information is arranged in the following order: ? absolute maximum ratings ? d.c. electrical characteristics ? data retention supp ly voltage in stop mode ? stop mode release timing when initiated by an external interrupt ? stop mode release timing when initiated by a reset ? i/o capacitance ? a.c. electrical characteristics ? a/d converter electrical characteristics ? input timing for external interrupt ? input timing for reset ? serial data transfer timing ? oscillation characteristics ? oscillation stabilization time ? operating voltage range
electrical data s3c 9228/p9228 16- 2 table 16-1. absolute maximum ratings (t a = 25 c) parameter symbol conditions rating unit supply voltage v dd ? ? 0.3 to + 6.5 v input voltage v in ports 0 ?6 ? 0.3 to v dd + 0.3 v output voltage v o ? ? 0.3 to v dd + 0.3 v output current high i oh one i/o pin active ? 15 ma all i/o pins active ? 60 output current low i ol one i/o pin active + 30 ma total pin current for ports + 100 operating temperature t a ? ? 25 to + 85 c storage temperature t stg ? ? 65 to + 150 c table 16-2. d.c. electrical characteristics (t a = ? 25 c to + 85 c, v dd = 2.0 v to 5.5 v) parameter symbol conditions min typ max unit operating voltage v dd fx = 0.4?4mhz, fxt = 32.8khz 2.0 ? 5.5 v fx = 0.4?8mhz 2.7 ? 5.5 input high voltage v ih1 ports 4?6 0.7 v dd ? v dd v v ih2 ports 0?3, reset 0.8 v dd v dd v ih3 x in , x out and xt in , xt out v dd ? 0.1 v dd input low voltage v il1 ports 4?6 ? ? 0.3 v dd v v il2 ports 0?3, reset 0.2 v dd v il3 x in , x out , xt in , xt out 0.1 output high voltage v oh v dd = 4.5 to 5.5 v; all output ports; i oh = ?1 ma v dd ? 1.0 ? v dd v output low voltage v ol v dd = 4.5 to 5.5 v; all output ports; i ol = 10 ma ? ? 2.0 v input high leakage current i lih1 v i = v dd ; all input pins except x in , x out , xt in , xt out ? ? 3 m a i lih2 v i = v dd ; x in , x out , xt in , xt out 20
s3c9228/p9228 elect rical data 16- 3 table 16-2. d.c. electrical characteristics (continued) (t a = ? 25 c to + 85 c, v dd = 2.0 v to 5.5 v) parameter symbol conditions min typ max unit input low leakage current i lil1 v i = 0 v; all input pins except reset , x out , xt in , xt out ? ? ?3 m a i lil2 v i = 0 v; x in , x out , xt in , xt out ?20 output high leakage current i loh v o = v dd all output pins ? ? 3 output low leakage current i lol v o = 0 v all output pins ? ? ?3 pull-up resistor r l1 v i = 0 v; v dd = 5v, t a = 25 c ports 0?6 25 47 100 k w v dd = 3v, t a = 25 c 50 90 150 r l2 v i = 0 v; v dd = 5v, t a = 25 c reset 150 250 400 v dd = 3v, t a = 25 c 300 500 700 oscillator feed back resistors r osc1 v dd = 5 v, t a = 25 c x in = v dd , x out = 0v 300 600 1500 k w r osc2 v dd = 5 v, t a = 25 c xt in = v dd , xt out = 0 v 1500 3000 4500 lcd voltage dividing resistor r lcd t a = 25 c 50 70 90 k w ? v lcd - comi ? voltage drop ( i = 0-7) v dc v dd = 2.7 v to 5.5 v - 15 m a per common pin ? ? 120 mv ? v lcd - seg x ? voltage drop (x = 0?19) v ds v dd = 2.7 v to 5.5 v - 15 m a per common pin ? ? 120 middle output voltage v lc2 v dd = 2.7 v to 5.5 v, lcd clock = 0hz, v lc1 = v dd 0.8v dd ?0.2 0.8v dd 0.8v dd + 0.2 v v lc3 0.6v dd ?0.2 0.6v dd 0.6v dd + 0.2 v lc4 0.4v dd ?0.2 0.4v dd 0.4v dd + 0.2 v lc5 0.2v dd ?0.2 0.2v dd 0.2v dd + 0.2 note: low leakage current is absolute value.
electrical data s3c 9228/p9228 16- 4 table 16-2. d.c. electrical characteristics (concluded) (t a = ? 25 c to + 85 c, v dd = 2.0 v to 5.5 v) parameter symbol conditions min typ max unit supply current (1) i dd1 run mode: v dd = 5 v 10% 8.0 mhz ? 6.0 12.0 ma crystal oscillator c1 = c2 = 22pf 4.19 mhz 3.0 6.0 v dd = 3 v 10% 8.0 mhz 2.5 5.0 4.19 mhz 1.5 3.0 i dd2 idle mode: v dd = 5 v 10% 8.0 mhz 1.3 3.0 crystal oscillator c1 = c2 = 22pf 4.19 mhz 1.0 2.0 v dd = 3 v 10% 8.0 mhz 0.8 1.6 4.19 mhz 0.4 0.8 i dd3 run mode: v dd = 3 v 10%, 32 khz crystal oscillator 15 30 m a i dd4 idle mode: v dd = 3 v 10%, 32 khz crystal oscillator 6 15 i dd5 stop mode; v dd = 5 v 10%, t a = 25 c 0.5 3 stop mode; v dd = 3 v 10%, t a = 25 c 0.3 2 notes: 1. supply current does not include current drawn through internal pull-up resistors, lcd voltage dividing resistors, and adc. 2. i dd1 and i dd2 include power consumption for subsystem clock oscillation. 3. i dd3 and i dd4 are current when main system clock oscillation stops and the subsystem clock is used. 4. i dd5 is current when main system clock and subsystem clock oscillation stops.
s3c9228/p9228 elect rical data 16- 5 table 16-3. data retention supply voltage in stop mode (t a = ? 25 c to + 85 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr ? 2.0 ? 5.5 v data retention supply current i dddr stop mode, t a = 25 c v dddr = 2.0 v ? ? 1 a execution of stop instruction idle mode (basic timer active) ~ ~ v dddr ~ ~ stop mode normal operating mode data retention mode v dd 0.8 v dd t wait note: t wait is the same as 16 x 1/bt clock. figure 16-1. stop mode release timing when initiated by an external interrupt
electrical data s3c 9228/p9228 16- 6 execution of stop instrction reset occurs ~ ~ v dddr ~ ~ stop mode oscillation stabilization time normal operating mode data retention mode t wait reset v dd 0.2 v dd 0.8 v dd note: t wait is the same as 16 1/bt clock. figure 16-2. stop mode release timing when initiated by a reset reset table 16-4. input/output capacitance (t a = 25 c, v dd = 0 v) parameter symbol conditions min typ max unit input capacitance c in f = 1 mhz; unmeasured pins are connected to v ss ? ? 10 pf output capacitance c out i/o capacitance c io
s3c9228/p9228 elect rical data 16- 7 table 16-5. a.c. electrical characteristics (t a = ? 25 c to + 85 c, v dd = 2.0 v to 5.5 v) parameter symbol conditions min typ max unit sck cycle time t kcy external sck source 1,000 ? ? ns internal sck source 1,000 sck high, low width t kh , t kl external sck source 500 internal sck source t kcy /2?50 si setup time to sck high t sik external sck source 250 internal sck source 250 si hold time to sck high t ksi external sck source 400 internal sck source 400 output delay for sck to so t kso external sck source ? ? 300 ns internal sck source 250 interrupt input, high, low width t inth , t intl all interrupt v dd = 3 v 500 700 ? ns reset input low width t rsl input v dd = 3 v 10 ? ? m s
electrical data s3c 9228/p9228 16- 8 table 16-6. a/d converter electrical characteristics (t a = ? 25 c to + 85 c, v dd = 2.7 v to 5.5 v, v ss = 0 v) parameter symbol conditions min typ max unit resolution ? 10 ? bit total accuracy vdd = 5.12 v ? ? 3 lsb integral linearity error ile fxx = 8 mhz ? ? 2 differential linearity error dle f con = fxx/4 ? ? 1 offset error of top eot ? 1 3 offset error of bottom eob ? 0.5 2 conversion time (1) t con 10-bit resolution 50 fxx/4, fxx = 8mhz 25 ? ? m s analog input voltage v ian ? v ss ? v dd v analog input impedance r an ? 2 1000 ? m w analog input current i adin v dd = 5 v ? ? 10 m a i adc v dd = 5 v ? 1 3 ma v dd = 3 v 0.5 1.5 v dd = 5 v when power down mode 100 500 na notes: 1. 'conversion time' is the time required from the moment a conversion operation starts until it ends. 2. i adc is an operating current during a/d conversion. t inth t intl 0.8 v dd 0.2 v dd note: the unit t cpu means one cpu clock period. external interrupt figure 16-3. input timing for external interrupts
s3c9228/p9228 elect rical data 16- 9 reset t rsl 0.2 v dd figure 16-4. input timing for reset reset t kh t kl 0.2v dd sck t kcy 0.8v dd 0.8v dd 0.2v dd t sik t ksi si so t kso output data figure 16-5. serial data transfer timing
electrical data s3c 9228/p9228 16- 10 table 16-7. main oscillation characteristics (t a = ? 25 c to + 85 c) oscillator clock configuration parameter test condition min typ max units crystal x in c1 x out main oscillation frequency 2.7 v ? 5.5 v 0.4 ? 8 mhz 2.0 v ? 5.5 v 0.4 ? 4 ceramic oscillator x in c1 x out main oscillation frequency 2.7 v ? 5.5 v 0.4 ? 8 2.0 v ? 5.5 v 0.4 ? 4 external clock x in x out x in input frequency 2.7 v ? 5.5 v 0.4 ? 8 2.0 v ? 5.5 v 0.4 ? 4 rc oscillator x in x out r frequency 5.0 v 0.4 ? 2 mhz frequency 3.0 v 0.4 ? 1 table 16-8. sub oscillation characteristics (t a = ? 25 c to + 85 c) oscillator clock configuration parameter test condition min typ max units crystal x in c1 x out sub oscillation frequency 2.0 v ? 5.5 v 32 32.768 35 khz external clock x in x out xt in input frequency 2.0 v ? 5.5 v 32 ? 100
s3c9228/p9228 elect rical data 16- 11 table 16-9. main oscillation stabilization time (t a = ? 25 c to + 85 c, v dd = 2.0 v to 5.5 v) oscillator test condition min typ max unit crystal fx > 1 mhz ? ? 30 ms ceramic oscillation stabilization occurs when vdd is equal to the minimum oscillator voltage ranage. ? ? 10 ms external clock x in input high and low width (t xh , t xl ) 62.5 ? 1250 ns t x t xl v dd -0.1 v 0.1 v x in 1/fx figure 16-6. clock timing measurement at x in
electrical data s3c 9228/p9228 16- 12 table 16-10. sub oscillation stabilization time (t a = ? 25 c to + 85 c, v dd = 2.0 v to 5.5 v) oscillator test condition min typ max unit crystal ? ? ? 10 s external clock xt in input high and low width (t xh , t xl ) 5 ? 15 m s t xth t xtl v dd -0.1 v 0.1 v xt in 1/fxt figure 16-7. clock timing measurement at xt in
s3c9228/p9228 elect rical data 16- 13 2 mhz 6.25 khz (main)/8.2 khz(sub) 1 2 6 supply voltage (v) instruction clock = 1/4n x oscillator frequency (n = 1, 2, 8, 16) 1.0 mhz instruction clock 8 mhz 4 mhz fx (main/sub oscillation frequency) 400 khz 2.7 5.5 400 khz (main)/32.8 khz(sub) figure 16-8. operating voltage range
electrical data s3c 9228/p9228 16- 14 notes
s3c9228/p9228 mechanical data 1 7- 1 17 mechanical data overview the s3c9228/p9228 microcontroller is currently available in a 42-pin sdip and 44-pin qfp package. note : dimensions are in millimeters. 39.50 max 39.10 0 .2 0.50 0.1 1.78 (1.77) 0.51 min 3.30 0.3 3.50 0.2 5.08 max 42-sdip-600 0-15 1.00 0.1 0.25 + 0.1 - 0.05 15.24 14.00 0 .2 #42 #22 #21 #1 figure 17-1. 42-sdip-600 package dimensions
mechanical data s3c9228/p9228 1 7- 2 44-qfp-1010b #44 note : dimensions are in millimeters. 10.00 0.2 13.20 0.3 10.00 0.2 13.20 0.3 #1 0.35 + 0.10 - 0.05 0.80 (1.00) 0.10 max 0.80 0.20 0.05 min 2.05 0.10 2.30 max 0.15 + 0.10 - 0.05 0-8 figure 17-2. 44-qfp-1010b package dimensions
s3c9228/p9228 S3P9228 otp 18- 1 18 S3P9228 otp overview the S3P9228 single-chip cmos microcontroller is the otp (one time programmable) version of the s3c9228 microcontroller. it has an on-chip otp rom instead of masked rom. the eprom is accessed by serial data format. the S3P9228 is fully compatible with the s3c9228, both in function and in pin configuration. because of its simple programming requirements, the S3P9228 is ideal for use as an evaluation chip for the s3c9228. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 s3c9228 (44-qfp) p1.0/ad0/int p1.1/ad1/int sdat /p1.2/ad2/int sclk /p1.3/ad3/int v dd /v dd v ss /v ss x out x in v pp /test xt in xt out reset reset / reset p2.3 p2.2/si seg0/p2.1/so seg1/p2.0/sck seg2/p3.1/intp seg3/p3.0/intp seg4/p4.0 seg5/p4.1 seg6/p4.2 seg7/p4.3 33 32 31 30 29 28 27 26 25 24 23 com5/seg18/p5.6 com6/seg17/p5.5 com7/seg16/p5.4 seg15/p5.3 seg14/p5.2 seg13/p5.1 seg12/p5.0 seg11/p4.7 seg10/p4.6 seg9/p4.5 seg8/p4.4 44 43 42 41 40 39 38 37 36 35 34 p0.5 p0.4 p0.3/buz/int p0.2/int p0.1/t1clk/int p0.0/taout/int com0/p6.3 com1/p6.2 com2/p6.1 com3/p6.0 com4/seg19/p5.7 figure 18-1. S3P9228 44-qfp pin assignments
S3P9228 otp s3c9228/p9228 18- 2 com1/p6.2 com0/p6.3 p0.0/taout/int p0.1/t1clk/int p0.2/int p0.3/buz/int p1.0/ad0/int p1.1/ad1/int sdat /p1.2/ad2/int sclk /p1.3/ad3/int v dd /v dd v ss /v ss x out x in v pp /test xt in xt out reset reset / reset p2.3 p2.2/si seg0/p2.1/so s3c9228 (42-sdip) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 com2/p6.1 com3/p6.0 com4/seg19/p5.7 com5/seg18/p5.6 com6/seg17/p5.5 com7/seg16/p5.4 seg15/p5.3 seg14/p5.2 seg13/p5.1 seg12/p5.0 seg11/p4.7 seg10/p4.6 seg9/p4.5 seg8/p4.4 seg7/p4.3 seg6/p4.2 seg5/p4.1 seg4/p4.0 seg3/p3.0/intp seg2/p3.1/intp seg1/p2.0/sck 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 figure 18-2. S3P9228 42-sdip pin assignments
s3c9228/p9228 S3P9228 otp 18- 3 table 18-1. descriptions of pins used to read/write the eprom main chip during programming pin name pin name pin no. i/o function p1.2 sdat 3 (9) i/o serial data pin. output port when reading and input port when writing. can be assigned as a input/push-pull output port. p1.3 sclk 4 (10) i/o serial clock pin. input only pin. test v pp (test) 9 (15) i power supply pin for eprom cell writing (indicates that otp enters into the writing mode). when 12.5 v is applied, otp is in writing mode and when 5 v is applied, otp is in reading mode. (option) reset reset 12 (18) i chip initialization v dd /v ss v dd /v ss 5/6 (11/12) i logic power supply pin. v dd should be tied to + 5 v during programming. note : parentheses indicate pin number for 42-sdip package. table 18-2. comparison of S3P9228 and s3c9228 features characteristic S3P9228 s3c9228 program memory 8 kbyte eprom 8 kbyte mask rom operating voltage (v dd ) 2.0 v to 5.5 v 2.0 v to 5.5 v otp programming mode v dd = 5 v, v pp (test)=12.5v pin configuration 44-qfp, 42-sdip 44-qfp, 42-sdip eprom programmability user program 1 time programmed at the factory operating mode characteristics when 12.5 v is supplied to the v pp (test) pin of the s3p72c8, the eprom programming mode is entered. the operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in table 17-3 below. table 18-3. operating mode selection criteria v dd v pp (test) reg/mem address (a15-a0) r/w mode 5 v 5 v 0 0000h 1 eprom read 12.5 v 0 0000h 0 eprom program 12.5 v 0 0000h 1 eprom verify 12.5 v 1 0e3fh 0 eprom read protection note : "0" means low level; "1" means high level.
S3P9228 otp s3c9228/p9228 18- 4 table 18-4. d.c. electrical characteristics (t a = ? 25 c to + 85 c, v dd = 2.0 v to 5.5 v) parameter symbol conditions min typ max unit supply current (1) i dd1 run mode: v dd = 5 v 10% 8.0 mhz ? 6.0 12.0 ma crystal oscillator c1 = c2 = 22pf 4.19 mhz 3.0 6.0 v dd = 3 v 10% 8.0 mhz 2.5 5.0 4.19 mhz 1.5 3.0 i dd2 idle mode: v dd = 5 v 10% 8.0 mhz 1.3 3.0 crystal oscillator c1 = c2 = 22pf 4.19 mhz 1.0 2.0 v dd = 3 v 10% 8.0 mhz 0.8 1.6 4.19 mhz 0.4 0.8 i dd3 run mode: v dd = 3 v 10%, 32 khz crystal oscillator 15 30 m a i dd4 idle mode: v dd = 3 v 10%, 32 khz crystal oscillator 6 15 i dd5 stop mode; v dd = 5 v 10%, t a = 25 c 0.5 3 stop mode; v dd = 3 v 10%, t a = 25 c 0.3 2 notes: 1. supply current does not include current drawn through internal pull-up resistors, lcd voltage dividing resistors, and adc. 2. i dd1 and i dd2 include power consumption for subsystem clock oscillation. 3. i dd3 and i dd4 are current when main system clock oscillation stops and the subsystem clock is used. 4. i dd5 is current when main system clock and subsystem clock oscillation stops.
s3c9228/p9228 S3P9228 otp 18- 5 2 mhz 6.25 khz (main)/8.2 khz(sub) 1 2 6 supply voltage (v) instruction clock = 1/4n x oscillator frequency (n = 1, 2, 8, 16) 1.0 mhz instruction clock 8 mhz 4 mhz fx (main/sub oscillation frequency) 400 khz 2.7 5.5 400 khz (main)/32.8 khz(sub) figure 18-3. standard operating voltage range
S3P9228 otp s3c9228/p9228 18- 6 notes
s3c9228/p9228 devel opment tools 19- 1 19 development tools overview samsung provides a powerful and easy-to-use development support system in turn key form. the development support system is configured with a host system, debugging tools, and support software. for the host system, any standard computer that operates with ms-dos as its operating system can be used. one type of debugging tool including hardware and software is provided: the sophisticated and powerful in-circuit emulator, smds2+, for s3c7, s3c8, s3c9 families of microcontrollers. the smds2+ is a new and improved version of smds2. samsung also offers support software that includes debugger, assembler, and a program for setting options. shine samsung host interface for in-circuit emulator, shine, is a multi-window based debugger for smds2+. shine provides pull-down and pop-up menus, mouse support, function/hot keys, and context-sensitive hyper-linked help. it has an advanced, multiple-windowed user interface that emphasizes ease of use. each window can be sized, moved, scrolled, highlighted, added, or removed completely. sama assembler the samsung arrangeable microcontroller (sam) assembler, sama, is a universal assembler, and generates object code in standard hexadecimal format. assembled program code includes the object code that is used for rom data and required smds program control data. to assemble programs, sama requires a source file and an auxiliary definition (def) file with device specific information. sasm86 the sasm86 is an relocatable assembler for samsung's s3c9-series microcontrollers. the sasm86 takes a source file containing assembly language statements and translates into a corresponding source code, object code and comments. the sasm86 supports macros and conditional assembly. it runs on the ms-dos operating system. it produces the relocatable object code only, so the user should link object file. object files can be linked with other object files and loaded into memory. hex2rom hex2rom file generates rom code from hex file which has been produced by assembler. rom code must be needed to fabricate a microcontroller which has a mask rom. when generating the rom code (.obj file) by hex2rom, the value ?ff? is filled into the unused rom area up to the maximum rom size of the target device automatically. target boards target boards are available for all s3c9-series microcontrollers. all required target system cables and adapters are included with the device-specific target board.
development tools s3c9228/p9228 19- 2 bus smds2+ rs-232c pod probe adapter prom/otp writer unit ram break/display unit trace/timer unit sam8 base unit power supply unit ibm-pc at or compatible tb9228 target board eva chip target application system figure 19-1. smds product configuration (smds2+)
s3c9228/p9228 devel opment tools 19- 3 tb9228 target board the tb9228 target board is used for the s3c9228 microcontroller. it is supported by the smds2+ development system. tb9228 sm1347a gnd v cc to user_v cc off on smds2 smds2+ j101 42sdip j102 44qfp 1 5 15 21 10 42 40 25 22 30 35 1 5 15 22 10 44 40 30 23 35 25 20 p2 25 160 30 20 10 1 150 140 130 50 60 70 80 90 100 110 120 c14 reset r1 d1 c1 c11 u2 r7 r8 y1 c7 cb + c9 c10 j1 c3 c4 c5 c6 t1 t2 t3 t4 idle + stop + r5 r4 c20 t16 t15 t14 t13 t12 t11 t10 t9 20 10 1 51 76 26 rev.0 '2002.03.30 cn1 figure 19-2. tb9228 target board configuration
development tools s3c9228/p9228 19- 4 table 19-1. power selection settings for tb9228 "to user_v cc " settings operating mode comments to user_v cc off on target system smds2/smds2+ tb9228 v cc v ss v cc the smds2/smds2+ supplies v cc to the target board (evaluation chip) and the target system. to user_v cc off on target system smds2/smds2+ tb9228 external v cc v ss v cc the smds2/smds2+ supplies v cc only to the target board (evaluation chip). the target system must have its own power supply. note : the following symbol in the "to user_v cc " setting column indicates the electrical short (off) configuration:
s3c9228/p9228 devel opment tools 19- 5 smds2+ selection (sam8) in order to write data into program memory that is available in smds2+, the target board should be selected to be for smds2+ through a switch as follows. otherwise, the program memory writing function is not available. table 19-2. the smds2+ tool selection setting "sw1" setting operating mode smds2 smds2+ target board r/w r/w smds2+ table 19-3. using single header pins as the input path for external trigger sources target board part comments external triggers ch1 ch2 connector from external trigger sources of the application system you can connect an external trigger source to one of the two external trigger channels (ch1 or ch2) for the smds2+ breakpoint and trace functions. idle led the green led is on when the evaluation chip (s3e9220) is in idle mode. stop led the red led is on when the evaluation chip (s3e9220) is in stop mode.
development tools s3c9228/p9228 19- 6 j101 42-sdip j102 44-qfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 43 44 45 46 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 50 49 48 47 p6.2 p6.3 p0.0 p0.1 p0.2 p0.3 p1.0 p1.1 p1.2 p1.3 user_vcc vss nc nc vss nc nc demo_rstb p2.3 p2.2 p2.1 nc nc nc nc p6.1 p6.0 p5.7 p5.6 p5.5 p5.4 p5.3 p5.2 p5.1 p5.0 p4.7 p4.6 p4.5 p4.4 p4.3 p4.2 p4.1 p4.0 p3.0 p3.1 p2.0 nc nc nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 45 46 47 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 50 49 48 p1.0 p1.1 p1.2 p1.3 user_vcc vss nc nc vss nc nc demo_rstb p2.3 p2.2 p2.1 p2.0 p3.1 p3.0 p4.0 p4.1 p4.2 p4.3 nc nc nc p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 p6.3 p6.2 p6.1 p6.0 p5.7 p5.6 p5.5 p5.4 p5.3 p5.2 p5.1 p5.0 p4.7 p4.6 p4.5 p4.4 nc nc nc figure 19-3. connectors (j101, j102) for tb9228
s3c9228/p9228 devel opment tools 19- 7 target board target system target cable for connector part name: ap42sd order code: sm6538 j101 1 42 21 22 j101 1 42 21 22 50-pin dip connector figure 19-4. s3c9228 probe adapter for 42-sdip package target board target system 50-pin connector target cable for 50-pin connector part name: ap50d-a order code: sm6305 50-pin connector j102 1 44 22 23 j102 1 44 22 23 figure 19-5. s3c9228 probe adapter for 44-qfp package
development tools s3c9228/p9228 19- 8 notes

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